Duty Correction Circuit With Frequency-Aware Clock Transition Control
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Solution Overview
Problem
Conventional duty correction circuits require a long time to complete duty correction and have limitations in accurately detecting clock duty and frequency range, due to offset issues and limited frequency range for correction.
Innovation Solution
A duty correction circuit comprising a clock buffer, swing level conversion block, duty control block, and current control block, which generates duty and frequency information to control the transition time of the clock logic value, using parallel and series current paths to adjust current flow based on frequency and duty information, allowing for accurate and rapid duty correction across a wide frequency range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a general duty correction circuit compares high pulse width with low pulse width of a clock, then duty correction is performed, but a long time is required until duty correction is completed
Solution Approach 1:
The duty correction circuit is divided into multiple functional blocks: a clock buffer for signal conditioning, a swing level conversion block for voltage level adaptation, a duty control block for generating duty and frequency information, and a current control block for precise timing control. This segmentation allows each block to perform its specific function efficiently, reducing overall correction time while maintaining accuracy
Solution Approach 2:
The current control block dynamically adjusts the time point at which the logic value of the buffer clock transitions based on real-time duty information and frequency information. This dynamic control enables the circuit to adapt to different clock frequencies and duty ratios, completing correction faster across varying conditions
2Measurement precision
If offset exists in the duty correction circuit, then duty detection is performed, but accurate detection of clock duty is difficult
Solution Approach 1:
A swing level conversion block is introduced as an intermediary between the clock buffer and the duty control block. This intermediary converts the buffer clock to an internal clock with proper voltage levels, ensuring clean signal transitions that minimize offset effects and enable accurate duty detection without compromising reliability
Solution Approach 2:
The circuit changes the voltage level parameter of the clock signal through the swing level conversion block, transforming it from buffer clock levels to internal clock levels. This parameter change ensures that the signal is at the optimal voltage level for accurate duty detection, eliminating offset-related detection errors
3Adaptability or versatility
If conventional duty correction circuit is used, then duty correction is performed, but frequency range of clock subject to duty correction is limited
Solution Approach 1:
The duty control block generates both duty information and frequency information from the internal clock parameters. The current control block then uses both types of information to control the transition timing. This multi-functional approach allows the circuit to handle a wide frequency range while maintaining precise duty correction through frequency-aware control
Data Source
AI summary
A duty correction circuit includes a clock buffer configured to buffer an input clock and generate a buffer clock, a swing level conversion block configured to generate an internal clock, which transitions to levels of a sync voltage and a power supply voltage, in response to a voltage level of the buffer clock, a duty control block configured to generate duty information and frequency information by using a high pulse width and a low pulse width of the internal clock, and a current control block configured to control a time point, at which a logic value of the buffer clock transitions, in response to the duty information and the frequency information. The current control block includes a plurality of first current paths coupled in parallel to one another in order to control the time point at which the logic value of the buffer clock transitions.