Duty Correction Circuit for Multi-Phase Clock Phase Errors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-frequency clock signals used in semiconductor devices for data transmission can lead to performance issues due to phase differences and duty ratio errors in multi-phase clock signals, which existing technologies have not effectively addressed.
Innovation Solution
A duty correction device that includes a clock generation circuit, correction pulse generation circuits, and a duty correction circuit to detect phase differences between multi-phase clock signals and adjust the duty cycle of the reference clock signal based on detected phase differences, thereby minimizing duty ratio errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-frequency clock signals are used for data transmission, then data transmission speed is improved, but phase differences and duty ratio errors in multi-phase clock signals worsen performance
Solution Approach 1:
The patent changes the parameters of clock signals by generating multiple divided clock signals with different phase offsets from a reference clock signal. The duty correction circuit dynamically adjusts the duty cycle of the reference clock signal based on detected phase differences, transforming the clock signal characteristics to maintain reliable data transmission at high frequencies.
Solution Approach 2:
The patent implements a feedback mechanism where the duty correction circuit detects phase differences between the reference clock signal and divided clock signals, then uses this detection result to control and adjust the duty cycle of the reference clock signal. This closed-loop feedback system continuously corrects duty ratio errors that would otherwise degrade performance at high transmission speeds.
2Reliability
If multi-phase clock signals are used to compensate for high-frequency effects, then data transmission reliability is improved, but duty ratio errors and phase differences worsen
Solution Approach 1:
The duty correction circuit continuously detects phase differences between clock signals and uses this feedback to adjust the duty cycle of the reference clock signal, thereby compensating for duty ratio errors that occur when using multi-phase clock signals for reliable data transmission.
Solution Approach 2:
The clock generation circuit proactively generates multiple divided clock signals with predetermined phase offsets before data transmission occurs. This preliminary preparation of phase-divided clock signals allows the system to compensate for high-frequency effects while the duty correction circuit subsequently fine-tunes the duty ratios to maintain accuracy.
3Manufacturing precision
If duty correction operation is performed based on phase difference detection, then duty ratio accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the clock signal generation into multiple divided clock signals with different phase offsets, allowing the duty correction operation to focus on adjusting a single reference clock signal based on phase difference detection from these segmented clock components.
Solution Approach 2:
The duty correction circuit serves multiple functions: it detects phase differences between clock signals, determines the appropriate duty cycle adjustments based on these detections, and controls the reference clock signal generation. This multi-functionality consolidates what could be multiple separate circuits into a single integrated duty correction unit.
Data Source
AI summary
A duty correction device includes a clock generation circuit, first and second correction pulse generation circuits, and a duty correction circuit. The clock generation circuit generates first to third divided clock signals, each having a phase offset from a reference clock signal. The first correction pulse generation circuit generates a first correction pulse by detecting a phase difference between a delayed clock signal and the first and second divided clock signals. The second correction pulse generation circuit generates a second correction pulse by detecting a phase difference between the second and third divided clock signals. The duty correction circuit checks whether the first and second correction pulses are generated at a preset logic level of the reference clock signal, and reflects the first or second correction pulses in a duty correction operation for the reference clock signal according to a result of the check.