Duty Correction Counting Circuit for Fast Locking and Fine Tuning
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Solution Overview
Problem
Existing duty correction circuits in semiconductor devices face challenges in balancing locking time and error correction, with binary search methods offering short locking times but large duty error changes, and linear search methods providing long locking times but small duty error corrections, leading to increased complexity when trying to implement both methods in a single circuit.
Innovation Solution
A counting circuit and duty correction circuit that selectively use either binary or linear search methods by controlling the toggling of counting clocks and adjusting duty correction codes, allowing for minimal area occupation and reduced error probability by switching between methods based on operational needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If binary search method is used to correct duty error, then locking time is shortened, but duty error changes occur in large units leading to reduced precision
Solution Approach 1:
The duty correction operation is divided into two distinct phases: initial duty correction using binary search method for rapid locking, and fine duty correction using linear search method for precise adjustment. This segmentation allows each phase to use the most appropriate algorithm for its specific requirements, resolving the contradiction between speed and precision.
Solution Approach 2:
The invention dynamically switches between binary search and linear search methods based on the current duty error magnitude. When duty error exceeds a threshold, binary search is used for fast correction; when duty error is within the threshold, linear search takes over for fine-tuning. This dynamic adaptation optimizes both locking time and precision throughout the correction process.
2Measurement precision
If linear search method is used to correct duty error, then duty error correction precision is improved, but locking time is extended
Solution Approach 1:
The duty correction operation is divided into two distinct phases: initial duty correction using binary search method for rapid locking, and fine duty correction using linear search method for precise adjustment. This segmentation allows each phase to use the most appropriate algorithm for its specific requirements, resolving the contradiction between speed and precision.
Solution Approach 2:
The invention dynamically switches between binary search and linear search methods based on the current duty error magnitude. When duty error exceeds a threshold, binary search is used for fast correction; when duty error is within the threshold, linear search takes over for fine-tuning. This dynamic adaptation optimizes both locking time and precision throughout the correction process.
3Adaptability or versatility
If both binary search method and linear search method are implemented in a single circuit, then both advantages can be utilized, but device complexity increases
Solution Approach 1:
The invention uses a single counting circuit that can perform both binary search and linear search operations by dynamically controlling the counting clock toggling. The same hardware infrastructure supports both correction methods, eliminating the need for separate circuits and reducing overall device complexity while maintaining versatility.
Solution Approach 2:
The invention dynamically switches between binary search and linear search methods based on the current duty error magnitude. When duty error exceeds a threshold, binary search is used for fast correction; when duty error is within the threshold, linear search takes over for fine-tuning. This dynamic adaptation optimizes both locking time and precision throughout the correction process.
Data Source
AI summary
A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result.


