Duty Cycle Correction Circuit With Adaptive Gain Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional analog duty cycle correction circuits face challenges in maintaining accuracy and reducing settling time due to leakage currents when powered off, leading to increased settling time when restored to active mode, and there is a trade-off between settling time and accuracy due to fixed current gain.
Innovation Solution
A digital duty cycle correction circuit incorporating a duty error detector, error corrector, analog to digital buffer, and duty error correction signal generator, which adjusts current gain dynamically based on detected duty errors to improve accuracy and reduce settling time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If current gain is increased to lessen settling time, then settling time is reduced, but duty cycle correction accuracy deteriorates due to error after settling
Solution Approach 1:
The patent applies dynamics by making the current gain adjustable rather than fixed. The duty cycle correction circuit includes a current gain adjustment unit that dynamically changes the current gain based on the correction amount. When the duty cycle error is large, the current gain is set higher to reduce settling time; when the error is small, the current gain is reduced to improve correction accuracy, thus resolving the trade-off between settling time and accuracy.
2Reliability
If capacitor capacity is increased to store duty error information during power down mode, then information retention is improved, but settling time increases when restored to active mode
Solution Approach 1:
The patent extracts the duty error information storage function from the capacitor and implements it using a digital register. The register stores the duty error information in digital form during power down mode, avoiding the leakage current problem of capacitors. When restored to active mode, the stored digital information is quickly converted to analog form, significantly reducing settling time while maintaining information retention reliability.
Solution Approach 2:
The patent replaces the analog capacitor-based storage mechanism with a digital register-based storage mechanism. This substitution eliminates the fundamental limitation of capacitor leakage current, allowing duty error information to be retained accurately during power down mode without requiring large capacitor capacity, thereby reducing settling time upon restoration.
3Reliability
If analog duty cycle correction circuit is used, then duty cycle correction is achieved, but information on duty error is damaged by leakage current during power down mode
Solution Approach 1:
The patent replaces the analog capacitor storage mechanism with a digital register storage mechanism. The digital register does not suffer from leakage current like analog capacitors, enabling reliable retention of duty error information during power down mode without energy loss, thus resolving the contradiction between reliability and energy loss.
Data Source
AI summary
A duty cycle correction circuit may include an error corrector adapted to correct duty cycles of first differential analog clock signals input to a pair of input terminals based on duty cycle correction signals input to a pair of control terminals and to output second differential analog clock signals having corrected duty cycles through a pair of output terminals, an analog to digital buffer adapted to convert the second differential analog clock signals to differential digital clock signals, a duty error detector adapted to detect duty cycles of the differential digital clock signals and to output a N bit digital signal, and a duty error correction signal generator adapted to output differential control current signals having current gains controlled based on the second differential analog clock signals and the N bit digital signal to the pair of control terminals as the duty cycle correction signals.