Duty Cycle Detector Using Charge Sharing for Fast Low-Noise Sensing
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Solution Overview
Problem
Existing duty cycle detectors are slow due to the need for lowpass filters to accurately extract the duty cycle, and they are prone to low-frequency noise, such as flicker noise, which degrades detection accuracy.
Innovation Solution
A duty cycle detection method and circuit that uses a current source and a four-phase sequential timing scheme to charge and discharge capacitors, enabling charge sharing between them, which allows for speedy detection and reduces noise by converting it into common-mode noise that can be suppressed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a lowpass filter is used to extract the DC level of a clock to accurately detect duty cycle, then measurement precision is improved, but the detector becomes slow due to long settling time
Solution Approach 1:
The patent segments the duty cycle detection process into four distinct phases (first phase, second phase, third phase, fourth phase) that operate sequentially within each clock cycle. This segmentation allows the circuit to perform different operations (current steering to different capacitors, charge sharing between capacitors) in each phase, enabling accurate duty cycle measurement without requiring a slow lowpass filter, thus resolving the contradiction between measurement precision and detection speed.
2Measurement precision
If an integration circuit is used to generate voltage proportional to clock high state duration, then duty cycle detection is achieved, but low-frequency flicker noise degrades detection accuracy
Solution Approach 1:
The patent converts the harmful flicker noise into a beneficial common-mode signal. By using four capacitors (first, second, third, fourth capacitors) and implementing charge sharing operations where noise appears equally on paired capacitors, the circuit transforms the noise into a common-mode component that can be rejected by differential readout, thereby improving measurement precision while utilizing the noise characteristics rather than merely suppressing them.
Solution Approach 2:
The patent merges the functions of multiple capacitors and switches into a unified charge-redistribution architecture. The first and second capacitors are merged with the third and fourth capacitors through charge sharing operations, allowing the circuit to process duty cycle information while canceling out noise through the combined effect of multiple storage elements working together in a coordinated manner.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution achieves speedy duty cycle detection, reducing the time required to detect the duty cycle to just two cycles of the clock, while also effectively mitigating noise, thereby improving detection accuracy.
Implementation Method 1
steer the first current onto a first capacitor and enabling charge sharing between a second capacitor and a fourth capacitor
Implementation Method 2
enabling charge sharing between a second capacitor and a fourth capacitor when the clock is in a first state
Data Source
AI summary
A duty cycle detector includes a current steering network configured to steer a first current into a second current to charge a first capacitor when a clock is in a first state, and to steer the first current into a third current to charge a second capacitor when the clock is in a second state; a first charge sharing switch configured to enable charge sharing between the first capacitor and a third capacitor when the clock is in the second state; a second charge sharing switch configured to enable charge sharing between the second capacitor and a fourth capacitor when the clock is in the first state; a first discharging network configured to discharge the first capacitor when the clock is in a first state; and a second discharging network configured to discharge the second capacitor when the clock is in a second state.