Duty-Cycle Phase Shift Circuit for Precise Clock De-Skew
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Solution Overview
Problem
Conventional de-skew circuits in high-density multi-lane forwarded-clock links face challenges in accurately aligning received clocks with data signals, particularly due to power consumption and inefficiencies in duty-cycle correction and phase shifting, which affect the performance of gigabit receivers.
Innovation Solution
A duty-cycle corrector phase shift (DCCPS) circuit is introduced, comprising a voltage-controlled delay line (VCDL) circuit, a duty-cycle corrector (DCC) circuit, an error amplifier circuit, and DC sampler circuits, which work together to adjust the duty cycle and phase shift of input clock signals to achieve a 50% duty cycle and specific phase shifts like 90 or 270 degrees, optimizing clock alignment while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DLL or PLL circuits are used in de-skew circuits, then clock alignment can be achieved, but power consumption increases and circuit complexity increases
Solution Approach 1:
The patent extracts and separates the duty-cycle correction function from the phase-locked loop circuit. By using a dedicated duty-cycle corrector circuit with simple delay elements and logic gates to correct duty cycle before the PLL, the power-consuming continuous phase adjustment of the PLL is eliminated for duty-cycle purposes, reducing overall power consumption while maintaining clock alignment precision.
Solution Approach 2:
The de-skew circuit is segmented into distinct functional blocks: a duty-cycle corrector circuit that handles duty-cycle adjustment separately, and a PLL circuit that handles phase alignment. This segmentation allows each circuit to be optimized independently, with the duty-cycle corrector using minimal power for its specific function.
2Measurement precision
If conventional DLL or PLL circuits are used in de-skew circuits, then clock alignment can be achieved, but device complexity increases
Solution Approach 1:
The patent extracts the duty-cycle correction functionality from the complex PLL circuit and implements it in a separate, simpler duty-cycle corrector circuit. This corrector uses basic delay elements and logic gates instead of the complex feedback and phase-detection mechanisms of a full PLL, reducing overall device complexity while maintaining alignment precision.
3Device complexity
If duty cycle is not corrected properly, then circuit operation is simplified, but clock alignment precision deteriorates
Solution Approach 1:
The duty-cycle corrector circuit performs preliminary duty-cycle correction on the input clock signal before it enters the PLL circuit. By pre-adjusting the duty cycle to approximately 50%, the subsequent phase-locking operation can proceed more effectively, improving final alignment precision without adding complex operation to the overall system.
4Device complexity
If phase shifting is not optimized, then circuit operation is simpler, but bandwidth efficiency deteriorates
Solution Approach 1:
The duty-cycle corrector performs preliminary adjustment of the clock signal characteristics before phase locking occurs. This pre-adjustment optimizes the signal for subsequent phase shifting operations, enabling more efficient bandwidth utilization in the forwarded-clock link without requiring complex phase-shifting mechanisms.
Data Source
AI summary
One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.