Duty-Cycle Corrector With Clock Detection to Prevent Saturation
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Solution Overview
Problem
Existing duty-cycle correction methods in electronic devices are inadequate for maintaining a stable 50% duty-cycle of clock signals during operation, as they often saturate when the input clock signal is disabled, leading to distorted clock signals upon reactivation and potential loss of clock periods.
Innovation Solution
The implementation of a duty-cycle corrector circuit that includes a clock detector to disable duty-cycle correction when the input clock signal is disabled, using an integrator circuit and amplifier circuit to regulate the duty-cycle and prevent error signal saturation, ensuring accurate correction within a few clock cycles upon reactivation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If duty-cycle correction is continuously applied, then duty-cycle stability is improved, but error signal saturation occurs when input clock is disabled
Solution Approach 1:
The clock detector monitors the input clock signal in advance and disables the duty-cycle correction circuit before the error signal can saturate. This preliminary action prevents the harmful effect of saturation by anticipating the clock disable condition and proactively adjusting the correction circuit state.
Solution Approach 2:
The clock detector provides feedback about the input clock signal status to the duty-cycle correction circuit. This feedback mechanism allows the correction circuit to adapt its operation based on real-time clock signal conditions, preventing error signal saturation when the clock is disabled while maintaining duty-cycle stability when the clock is active.
2Measurement precision
If duty-cycle correction is applied after clock reactivation, then duty-cycle accuracy is improved, but clock period loss occurs during transition
Solution Approach 1:
The clock detector re-enables the duty-cycle correction circuit immediately upon detecting clock reactivation, performing the correction action in advance rather than after a delay. This preliminary reactivation minimizes the time during which clock periods could be lost while ensuring duty-cycle accuracy is restored.
Solution Approach 2:
The duty-cycle correction circuit maintains continuous operation by being rapidly re-enabled after clock reactivation. This continuity ensures that the useful correction action is never interrupted for extended periods, preventing both clock period loss and duty-cycle inaccuracy during the transition phase.
3Device complexity
If simple duty-cycle correction circuit is used, then device complexity is reduced, but inability to prevent error saturation occurs
Solution Approach 1:
The duty-cycle correction system is segmented into distinct functional blocks: a clock detector circuit and a duty-cycle correction circuit. This segmentation allows the simple correction circuit to operate reliably by delegating the clock monitoring and control functions to the dedicated clock detector, preventing error saturation without significantly increasing overall system complexity.
Data Source
AI summary
Electronic devices are disclosed. An electronic device may include a duty-cycle corrector configured to receive a clock signal. The duty-cycle corrector may also be configured to enable duty-cycle correction responsive to the clock signal being activated. Further, the duty-cycle corrector may be configured to disable the duty-cycle correction responsive to the clock signal being deactivated. Associated apparatuses and methods are also disclosed.