Duty Cycle Calibration Circuit for Low-Jitter Clock Doubling
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Solution Overview
Problem
Existing semiconductor circuits face issues with unqualified jitter and increased power consumption due to cascaded PLL circuits, particularly when used for clock distribution, which are exacerbated by dedicated power supplies and bumps.
Innovation Solution
A circuit and method utilizing a duty cycle calibration (DCC) device, phase adjusting device, and duty cycle measurement (DCM) device to generate and adjust a periodic output signal with a frequency twice that of the input signal, reducing the need for dedicated power supplies and power bumps, thereby minimizing power consumption and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cascaded PLL circuits are used to increase reference clock signal frequency, then frequency multiplication is achieved, but jitter increases and power consumption increases due to dedicated power supplies and bumps
Solution Approach 1:
The patent segments the frequency multiplication function into multiple digital circuit stages, where each stage performs a portion of the frequency doubling operation. This segmentation allows the system to achieve high frequency multiplication without requiring a single complex PLL circuit, thereby reducing jitter while maintaining the desired output frequency.
Solution Approach 2:
The patent implements a universal digital circuit design that can perform frequency multiplication without requiring dedicated power supplies and bumps for each PLL stage. The circuit uses shared power distribution and control mechanisms, making the system more compact and reducing overall power consumption while achieving the same frequency multiplication effect.
2Speed
If cascaded PLL circuits with dedicated power supplies and bumps are used, then frequency multiplication is achieved, but power consumption increases
Solution Approach 1:
The patent merges multiple PLL circuits into a single integrated digital circuit implementation. By combining the frequency multiplication functionality into one unified circuit block that shares power distribution networks, the design eliminates the need for multiple dedicated power supplies and bumps, thereby significantly reducing power consumption while maintaining the frequency multiplication capability.
Solution Approach 2:
The universal digital circuit design performs multiple functions (frequency doubling, duty cycle calibration, signal conditioning) within a single circuit architecture, eliminating the need for separate dedicated power supplies for each function. This multi-functional approach reduces overall power consumption while achieving the desired frequency multiplication.
3Reliability
If duty cycle calibration and measurement devices are added to adjust the periodic signal, then signal quality and bandwidth are improved, but device complexity increases
Solution Approach 1:
The patent merges the duty cycle calibration device and measurement device into the same circuit block that performs frequency multiplication. By integrating these functions rather than adding them as separate external components, the design improves signal quality and bandwidth while minimizing the increase in overall device complexity through shared circuitry and resources.
Data Source
AI summary
A circuit and a method for adjusting a periodic input signal are provided. The circuit includes a duty cycle calibration (DCC) device, a phase adjusting device, and a duty cycle measurement (DCM) device. The DCC device is configured to generate a first signal and a second signal in response to the periodic input signal. The first signal and the second signal have different phases. The phase adjusting device is configured to receive the first signal and the second signal to generate a third signal by combining the first signal and the second signal based on a selection signal. The DCM device is configured to measure and adjust a duty cycle of the third signal so that the selection signal is adjusted to generate a periodic output signal. A frequency of the periodic output signal is twice that of the periodic input signal.