Duty Cycle Correction Circuit for Mode-Dependent Clock Duty Drift
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Solution Overview
Problem
Semiconductor devices, such as DDR DRAM, face malfunctions due to changes in clock signal duty rates during normal operation modes, as the duty cycle correction circuit fails to maintain the desired 50:50 ratio caused by differing operation power voltages between duty training and normal operation modes.
Innovation Solution
A duty cycle correction circuit comprising a duty correction circuit, an information generation circuit, and a duty control circuit that compares operation power voltages across modes to generate a duty control code, ensuring the clock signal maintains a 50:50 duty rate by adjusting drive forces and voltage information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the duty cycle correction circuit uses a single duty control code for both duty training operation mode and normal operation mode, then the circuit structure is simple, but the duty rate of the clock signal changes in normal operation mode due to different operation power voltages, causing malfunction
Solution Approach 1:
The patent divides the operation modes into at least two segments: duty training operation mode and normal operation mode. For each mode, a separate duty control code is generated based on the respective operation power voltage characteristics. This segmentation allows the duty cycle correction circuit to apply mode-specific correction parameters, preventing duty rate drift when transitioning between modes with different power voltages.
Solution Approach 2:
The patent implements dynamic adaptation by generating duty control codes that are specific to each operation mode rather than using a fixed code. The duty cycle correction circuit dynamically selects and applies the appropriate duty control code based on the current operation mode, enabling the system to adapt to changing power voltage conditions and maintain stable duty rate performance.
2Reliability
If the duty cycle correction circuit generates mode-specific duty control codes, then the duty rate stability is improved, but the device complexity increases due to additional information generation circuits
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing duty control codes for different operation modes before actual operation. The information generation circuit generates duty control codes based on expected operation power voltage characteristics of each mode, so that when a mode is activated, the corresponding pre-generated duty control code is immediately available for application, avoiding real-time calculation complexity during operation.
Solution Approach 2:
The patent introduces an information generation circuit as an intermediary component that bridges the operation mode selection and the duty cycle correction function. This intermediary circuit generates appropriate duty control codes by comparing operation power voltage differences between modes, enabling the main duty cycle correction circuit to function properly without requiring complex internal modifications.
3Adaptability or versatility
If the operation power voltage changes between duty training mode and normal operation mode, then the circuit can operate in different modes, but the duty rate of the clock signal changes causing the semiconductor device to malfunction
Solution Approach 1:
The patent applies parameter changes by adjusting the duty control code parameter based on the operation mode and corresponding power voltage characteristics. When transitioning between duty training mode and normal operation mode, the system changes the duty control code parameter to compensate for power voltage differences, thereby maintaining consistent duty rate performance across different operational conditions.
Data Source
AI summary
A duty cycle correction circuit includes a duty correction circuit, an information generation circuit and a duty control circuit. The duty correction circuit corrects a duty rate of an input clock signal based on a duty control code to generate an output clock signal. The information generation circuit compares a difference between operation power voltages based on an operation mode to generate voltage information. The duty control circuit receives the voltage information from the information generation circuit and generates the duty control code that includes the voltage information based on a duty rate of the output clock signal.