Duty Cycle Calibration Circuit for Delay-Compensated Clock Edges
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Solution Overview
Problem
Existing duty cycle correction circuits fail to maintain a 50% duty cycle due to delays in electronic devices, affecting data transmission efficiency.
Innovation Solution
A duty cycle correction circuit comprising inverters, delayers, and adjustment circuits that process signals to eliminate delays between rising and falling edges, ensuring accurate duty cycle correction by generating correction signals based on the phase and delay differences between input signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If level conversion is applied to improve clock signal amplitude, then signal amplitude is improved, but duty cycle accuracy deteriorates due to delays in electronic devices
Solution Approach 1:
The patent applies preliminary action by introducing delay compensation mechanisms before the clock signal is used for data transmission. The circuit pre-calculates and compensates for the delays that will occur during level conversion, ensuring that the duty cycle remains accurate despite the upcoming signal processing operations.
Solution Approach 2:
The patent implements feedback by using the delayed clock signal itself to generate compensation signals. The circuit monitors the actual delay introduced by electronic devices and uses this information to adjust and correct the duty cycle, creating a closed-loop system that maintains precision despite signal amplitude improvements.
2Manufacturing precision
If delay compensation is applied to improve duty cycle accuracy, then duty cycle precision is improved, but circuit complexity increases
Solution Approach 1:
The patent applies universality by designing circuit components that perform multiple functions. The same circuit elements used for level conversion also participate in delay compensation and duty cycle correction, reducing the need for separate dedicated compensation circuits and thereby limiting the increase in overall circuit complexity.
Solution Approach 2:
The patent implements self-service by enabling the clock signal circuit to compensate for its own delays. The circuit uses its internal signals and components to automatically correct duty cycle errors without requiring external intervention or complex additional control mechanisms, thereby maintaining relatively simple circuit architecture.
Data Source
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AI summary
A duty cycle correction circuit 10 includes: a first inverter 101, a first delayer 102, and a first adjustment circuit 103. An input terminal of the first inverter 101 is configured to receive a first signal, and an output terminal of the first inverter 101 is configured to output a third signal. A first input terminal of the first adjustment circuit 103 is connected to the output terminal of the first inverter 101 and configured to receive the third signal, and an output terminal of the first adjustment circuit 103 is configured to output a first correction signal. An input terminal of the first delayer 102 is configured to input a second signal, and an output terminal of the first delayer 102 is connected to a second input terminal of the first adjustment circuit 103 and configured to output a fourth signal to the first adjustment circuit 103, wherein the fourth signal has a delay of a first time duration relative to the second signal. When the third signal and the fourth signal are at a high level, the first correction signal is at the high level. When the third signal and the fourth signal are at a low level, the first correction signal is at the low level.