Duty-Cycle Corrector Circuit for High-Frequency Clock Synchronization
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Solution Overview
Problem
Adjusting the duty-cycle of high-frequency internal clock signals in semiconductor devices like DRAMs is challenging while maintaining the original frequency, necessitating the use of divided clock signals to achieve accurate synchronization.
Innovation Solution
A semiconductor device configuration that includes a clock control circuit with a divider circuit generating divided clock signals, duty-cycle adjusters, and a DCA control circuit to adjust the timing of rising and falling edges of these signals, ensuring the duty-cycle is corrected and synchronized with external clock signals, thereby maintaining a 50% duty-cycle and uniform periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the duty-cycle of high-frequency internal clock signals is adjusted directly, then the duty-cycle accuracy improves, but it becomes difficult to maintain the original frequency
Solution Approach 1:
The patent divides the high-frequency internal clock signal into multiple lower-frequency divided clock signals. By adjusting the duty-cycle of these divided signals and then synthesizing them, the system achieves accurate duty-cycle control without directly manipulating the high-frequency signal, thus maintaining the original frequency integrity.
Solution Approach 2:
The patent introduces divided clock signals as intermediary elements between the high-frequency internal clock and the duty-cycle adjustment mechanism. These divided signals serve as mediators that can be easily adjusted in terms of duty-cycle while preserving the timing relationships needed to reconstruct the original high-frequency signal with correct duty-cycle.
2Manufacturing precision
If divided clock signals are used to adjust duty-cycle, then the duty-cycle accuracy improves, but the device complexity increases
Solution Approach 1:
The duty-cycle adjuster circuit is designed to handle multiple divided clock signals using a unified adjustment mechanism. This multi-functional approach allows the same circuit structure to adjust the duty-cycle of different divided signals, reducing overall circuit complexity compared to having separate adjustment circuits for each signal.
Solution Approach 2:
The patent combines the adjusted divided clock signals to reconstruct the internal clock signal with the desired duty-cycle. By merging the adjusted divided signals in a coordinated manner, the system achieves accurate duty-cycle control without requiring complex individual processing for each signal path.
3Manufacturing precision
If the timing of rising and falling edges is adjusted independently, then the duty-cycle control precision improves, but the synchronization difficulty increases
Solution Approach 1:
The patent employs a feedback mechanism where the adjusted divided clock signals are monitored and coordinated to ensure proper synchronization. The feedback loop detects timing relationships and adjusts the independent edge timing accordingly, maintaining synchronization while allowing precise duty-cycle control.
Solution Approach 2:
The system performs preliminary adjustment of the divided clock signals' timing before synthesizing them into the final internal clock signal. By pre-coordinating the rising and falling edges of divided signals and establishing their temporal relationships in advance, the synchronization complexity is managed during the division stage rather than during final synthesis.
Data Source
AI summary
Disclosed herein is an apparatus that includes: a first input node supplied with a first clock signal; a first clock path configured to output a delayed first clock signal, the first clock path including first and second delay elements coupled in series; a second clock path configured to output additional delayed first clock signal, the second clock path including third and fourth delay elements coupled in series; a first mixer circuit configured to interpolate the delayed first clock signal and the additional delayed first clock signal to reproduce an adjusted clock signal as the first clock signal; and a control circuit configured to control delay amounts of the first, second, third, and fourth delay elements with first, second, third, and fourth codes different from one another.