Duty Cycle Correction Circuit for Stable 50% Clock Timing
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Solution Overview
Problem
Dynamic random access memory (DRAM) systems face issues due to mismatched complementary clock signals (VCLK and /VCLK) leading to a shifted main clock signal (MCLK), affecting internal circuit clock signal margins due to device mismatch and temperature factors.
Innovation Solution
A duty cycle correction circuit comprising a frequency divider, duty cycle detector, and delay circuit that adjusts the falling edge of a clock signal to generate a correction clock signal, ensuring a 50% duty cycle by dividing the frequency of the clock signal and comparing voltage levels to generate a control signal for adjusting the delay time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complementary clock signals are used without correction, then the circuit operation is simple, but the clock signal duty cycle drifts due to device mismatch and temperature factors
Solution Approach 1:
The duty cycle detector continuously monitors the duty cycle of the clock signal and generates a control signal based on the detected duty cycle value. This control signal is fed back to the delay circuit to adjust the delay amount, thereby automatically correcting duty cycle drift. The feedback mechanism ensures the clock signal maintains a stable 50% duty cycle despite device mismatch and temperature variations.
Solution Approach 2:
The circuit uses its own clock signal to generate the control signal for correction. The duty cycle detector processes the clock signal itself to detect duty cycle deviations, and the delay circuit uses this information to adjust its own delay characteristic, making the system self-correcting without requiring external intervention.
2Reliability
If a duty cycle correction circuit is added, then the clock signal duty cycle stability is improved, but the device complexity increases
Solution Approach 1:
The correction circuit is divided into three functional modules: a frequency divider that divides the clock signal frequency, a duty cycle detector that detects duty cycle based on voltage comparison, and a delay circuit that adjusts delay amount. This segmentation allows each module to perform a specific function efficiently, reducing overall circuit complexity while achieving accurate duty cycle correction.
Solution Approach 2:
The delay circuit dynamically changes its delay parameter based on the control signal from the duty cycle detector. By adjusting the delay amount as a variable parameter rather than a fixed value, the circuit can adapt to different duty cycle conditions and maintain 50% duty cycle accuracy without requiring complex switching mechanisms.
Data Source
AI summary
A duty cycle correction circuit comprises a frequency divider, a duty cycle detector and a delay circuit. The frequency divider receives a first clock signal and divides the frequency of the first clock signal to generate a second clock signal. The duty cycle detector receives the second clock signal and a correction clock signal and generates a control signal according to the second clock signal and the correction clock signal. The delay circuit receives the first clock signal and the control signal and adjusts a delay time of a falling edge of the first clock signal according to the control signal to generate the correction clock.