Duty Cycle Correction Timing for Stable Clock Signal Toggling
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Solution Overview
Problem
Existing duty cycle correction methods in high-speed applications experience prolonged training times and unstable duty cycles due to delayed update timings, leading to potential logic function failures.
Innovation Solution
A duty cycle correction method and system that updates the duty cycle corrector before the next toggle of the clock signal, using a recorded training result to stabilize the duty cycle, thereby reducing changes during clock signal toggling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the duty cycle corrector is updated after receiving the data out command and performing training, then the training result can be recorded, but the duty cycle changes during clock signal toggle causing logic function failure
Solution Approach 1:
The patent applies preliminary action by updating the duty cycle corrector before the next toggle of the clock signal, rather than after receiving the data out command. This timing ensures that the duty cycle is stabilized in advance before the clock signal toggles, preventing logic function failures while maintaining efficient operation without extended training time
2Manufacturing precision
If the training is performed sequentially before data out, then the duty cycle can be corrected, but the overall operation time is prolonged
Solution Approach 1:
The training is performed as a preliminary action before the next clock signal toggle, ensuring duty cycle accuracy is achieved in advance. This allows the system to maintain high precision while avoiding sequential execution delays, as the training completes before the critical toggle event rather than adding to the overall operation timeline
3Measurement precision
If the duty cycle corrector is updated at time T1 after training completion, then the training result is recorded, but the duty cycle fluctuation causes performance inconsistency
Solution Approach 1:
The update is performed as a preliminary action before the next clock signal toggle, ensuring that the duty cycle is stabilized with the recorded training result in advance. This timing prevents duty cycle fluctuations during the toggle event, maintaining both measurement precision and operational stability without conflict
Data Source
AI summary
A duty cycle correction method and a duty cycle correction system, adapted for correcting a duty cycle of a clock signal by using a duty cycle corrector (DCC) in a high-capacity and high-performance semiconductor product such as a 3D NAND flash, are provided. In the method, training is performed on the DCC to correct the clock signal, and a training result is recorded after the training is finished; and the DCC is updated by the recorded training result before a next toggle of the clock signal.