Duty Cycle Adjuster Code Setting for Internal Clock Distortion

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Solution Overview

Problem

Existing semiconductor memory duty cycle adjuster circuits fail to accurately adjust the duty cycle of internal clocks, leading to potential erroneous operations due to duty cycle distortion.

Innovation Solution

A duty cycle adjuster circuit with a duty cycle monitor (DCM) and mode register features that allow precise adjustment of internal clock duty cycles by monitoring and compensating for duty cycle errors through programmable settings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If duty cycle adjuster circuits are used to adjust internal clock duty cycles, then duty cycle distortion is reduced, but the adjustment accuracy is insufficient leading to erroneous operations

Engineering Contradiction:

Improveoperation accuracyVSAvoidduty cycle adjustment precision

Core Design Contradiction:

ReliabilityVSMeasurement precision

Solution Approach 1:

The patent implements a feedback mechanism where the duty cycle monitor continuously measures the actual duty cycle of internal clocks and compares it against the target 50% duty cycle. Based on this feedback, the system automatically adjusts the duty cycle adjuster circuit to compensate for deviations, ensuring accurate duty cycle maintenance without manual intervention.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent replaces manual or coarse mechanical adjustment mechanisms with an electronic feedback control system. The duty cycle monitor and automatic adjustment circuitry substitute for imprecise mechanical adjusters, providing fine-grained electronic control over the duty cycle through voltage or current adjustments in the clock circuitry.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If duty cycle adjuster circuits are implemented, then clock timing is improved, but device complexity increases

Engineering Contradiction:

Improveclock timing accuracyVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the duty cycle monitor, control logic, and adjuster circuit into an integrated clock management unit. By combining these functions into a single modular block, the system reduces overall device complexity while maintaining accurate duty cycle control, as the integrated design shares common circuitry and control signals.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The duty cycle adjuster circuit is designed to be self-regulating through automatic feedback control. The system monitors its own performance and autonomously adjusts its parameters without external intervention, eliminating the need for complex external control mechanisms and simplifying the overall device architecture.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS12586621B2Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

Publication Date: 2026.03.24 LODESTAR LICENSING GROUP LLC

AI summary

Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.