Duty Cycle Correction for High Speed Clock Signal Integrity
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Solution Overview
Problem
The transmission of high speed clock signals between driver circuits in LED display panels is hindered by distortion due to non-ideal channel characteristics of printed circuit boards, leading to limitations in signal integrity and frequency, necessitating a novel transmission scheme.
Innovation Solution
A display control system with driver circuits connected in series, each equipped with a receiver, duty cycle correction circuit, and transmitter, which adjusts and transmits the duty cycle of the clock signal to maintain signal integrity and enable high speed clock transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high speed clock signal is transmitted between driver circuits through PCB traces, then the display operation speed can be increased, but the signal will suffer from higher distortion due to non-ideal channel characteristics
Solution Approach 1:
The system segments the clock signal transmission into multiple stages, with each driver circuit containing a transmitter that receives a clock signal from a previous driver circuit and transmits to a next driver circuit. This segmentation allows the high speed clock signal to be transmitted through series-connected driver circuits while managing distortion through intermediate duty cycle correction circuits.
Solution Approach 2:
A duty cycle correction circuit is introduced as an intermediary component between the transmitter and receiver in each driver circuit. This intermediary corrects the duty cycle of the transmitted clock signal, compensating for distortion introduced by PCB trace characteristics and enabling reliable high speed clock transmission across multiple driver circuits.
2Reliability
If a low speed clock signal is used for SPI communication between driver circuits, then signal integrity is maintained with lower channel loss, but the display operation speed is limited
Solution Approach 1:
The system changes the clock signal frequency parameter locally at each driver circuit. Each driver circuit receives a high speed clock signal from the previous driver circuit and uses it to generate the necessary operating frequencies for display data transmission, eliminating the need for PLL circuits while enabling high speed operation.
3Speed
If PLL circuits are used in each driver circuit to convert low speed clock to high speed clock, then high resolution display operation is enabled, but the circuit structure becomes complex with higher power consumption and larger circuit area
Solution Approach 1:
The invention extracts and removes the PLL circuit from each driver circuit by implementing a different approach: each driver circuit contains a transmitter that directly receives and transmits the high speed clock signal, with a duty cycle correction circuit to maintain signal quality. This eliminates the complex PLL structure while achieving the same high speed clock generation function.
Data Source
AI summary
A display control system includes a plurality of driver circuits connected in series. A driver circuit among the plurality of driver circuits includes a receiver, a duty cycle correction circuit and a transmitter. The receiver is configured to receive a first signal from a previous driver circuit among the plurality of driver circuits. The duty cycle correction circuit, coupled to the receiver, is configured to adjust a duty cycle of the first signal to generate a second signal. The transmitter, coupled to the duty cycle correction circuit, is configured to transmit the second signal to a next driver circuit among the plurality of driver circuits.