Duty Cycle Correction Device for Semiconductor Memory Clock Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional duty cycle correction devices for semiconductor memory chips, which employ delay circuits, have a poor correcting ability for achieving a 50% duty cycle in clock signals output from delay locked loop (DLL) circuits.
Innovation Solution
A duty cycle correction device that uses a phase mixer to combine and control the phases of two clock signals from a DLL circuit, with a control unit adjusting the mixing ratio to achieve a predetermined duty cycle, including a phase splitter, duty detection unit, combination unit, shift register, and phase detection unit to refine the mixing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a delay circuit is used to adjust the duty cycle of an internal clock output from a DLL circuit, then the duty cycle can be adjusted, but the correcting ability for the duty cycle is very poor
Solution Approach 1:
The patent changes the fundamental parameter of duty cycle correction from time-delay based adjustment to phase-mixing based adjustment. By using a phase mixer to combine multiple clock signals with different phases in specific ratios, the duty cycle can be precisely controlled through parameter adjustment rather than relying on delay circuit timing, thereby achieving superior correction precision and reliability
Solution Approach 2:
The patent replaces the mechanical/time-based delay circuit system with a signal processing system using phase mixers and duty cycle detectors. This substitution transforms the correction mechanism from physical time-delay to electrical signal mixing, enabling more precise and reliable duty cycle control through electronic parameter adjustment
Data Source
AI summary
Enclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop circuit. The duty cycle correction device includes a mixer for mixing phases of the first and second clock signals, thereby outputting a first signal, a phase splitter receiving the first signal and outputting a third clock signal, a duty detection unit receiving the third and fourth clock signals to detect a difference between duty cycles of the third and fourth clock signals, a combination unit for outputting a second signal, a shift register for outputting a first control signal, a phase detection unit receiving the first and second clock signals and outputting a second control signal representing a difference between duty cycles of the first and second clock signals. The mixer adjusts a mixing ratio by using the first and second control signals.