Duty Cycle Correction Circuit for Cascaded LTDI Clock Distortion
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Solution Overview
Problem
In cascaded Large Touch and Display Driver Integration (LTDI) systems, duty cycle distortion occurs due to resistance-capacitance (RC) effects in clock signals, leading to potential operational issues in touch screen display devices like smartphones and tablets, as the distortion accumulates across multiple ICs connected in cascade arrangements.
Innovation Solution
A dual-pronged duty cycle correction mechanism is introduced, comprising a Phase-Locked Loop (PLL)-based duty cycle correction circuit and a bypass duty cycle correction circuit, along with a multiplexer to select the output clock signal, ensuring corrected duty cycles and mitigating jitter accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple LTDI ICs are cascaded to handle larger or higher-resolution displays, then the driving capability is sufficient, but duty cycle distortion accumulates due to RC effects in long PCB traces
Solution Approach 1:
A duty cycle correction circuit is introduced as an intermediary component between the clock signal source and the cascaded LTDI ICs. This correction circuit actively compensates for the duty cycle distortion caused by RC effects in the PCB traces, ensuring that each IC receives a clock signal with the correct duty cycle despite the cumulative effects of long trace connections
Solution Approach 2:
The duty cycle correction circuit employs feedback mechanisms to continuously monitor and adjust the clock signal characteristics. By detecting duty cycle deviations and applying real-time corrections, the system maintains accurate timing signals throughout the cascaded IC configuration, preventing the accumulation of timing errors
2Manufacturing precision
If PLL-based duty cycle correction is used, then duty cycle distortion is corrected, but jitter accumulation may occur
Solution Approach 1:
The system dynamically switches between different duty cycle correction methods based on operating conditions. A multiplexer selects between PLL-based correction (when jitter is acceptable) and bypass correction (when minimal jitter is required), allowing the system to optimize performance based on the specific application requirements and signal conditions
Solution Approach 2:
The system changes the correction parameter by offering two distinct correction approaches: PLL-based correction that provides robust duty cycle accuracy but may introduce jitter, and bypass correction that minimizes jitter but has different correction characteristics. The multiplexer enables selection of the appropriate parameter set based on system requirements
3Reliability
If bypass duty cycle correction is used, then jitter accumulation is reduced, but duty cycle correction capability may be limited
Solution Approach 1:
The system dynamically switches between different duty cycle correction methods based on operating conditions. A multiplexer selects between PLL-based correction (when jitter is acceptable) and bypass correction (when minimal jitter is required), allowing the system to optimize performance based on the specific application requirements and signal conditions
Data Source
AI summary
A duty cycle correction device includes: a phase-locked Loop (PLL)-based duty cycle correction circuit, a bypass duty cycle correction circuit and a multiplexer. The PLL-based duty cycle correction circuit is configured to receive and correct an input clock signal to generate a PLL-based corrected signal. The bypass duty cycle correction circuit is configured to be clocked by the input clock signal to sample a logic signal at its input terminal to generate a bypass corrected signal. The multiplexer is coupled to the PLL-based duty cycle correction circuit and the bypass duty cycle correction circuit and is configured to select one of the PLL-based corrected signal, the bypass corrected signal and the input clock signal as an output clock signal.