Dual-Path Duty Cycle Correction for Cascaded LTDI Clock Signals
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Solution Overview
Problem
In cascaded Large Touch and Display Driver Integration (LTDI) systems, duty cycle distortion occurs due to resistance-capacitance (RC) effects in clock signals, leading to potential operational issues in touch screen display devices like smartphones and tablets, especially when multiple ICs are connected in cascade arrangements.
Innovation Solution
A dual-pronged duty cycle correction mechanism is introduced, comprising a Phase-Locked Loop (PLL)-based duty cycle correction circuit and a bypass duty cycle correction circuit, along with a multiplexer to select the output clock signal, ensuring corrected duty cycles and mitigating jitter accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple LTDI ICs are connected in cascade arrangement to drive larger displays, then the driving capability is improved, but duty cycle distortion accumulates due to RC effects
Solution Approach 1:
The duty cycle correction function is segmented into two independent circuits: PLL-based correction circuit and bypass correction circuit. Each circuit handles correction independently, allowing the system to maintain driving capability while correcting duty cycle distortion through selective activation of correction segments
Solution Approach 2:
The system changes the correction parameter by switching between two different correction mechanisms (PLL-based and bypass). The bypass circuit provides alternative correction path that avoids jitter accumulation while maintaining duty cycle correction, effectively changing how the correction is applied rather than increasing correction strength
2Manufacturing precision
If PLL-based duty cycle correction is used to correct clock signal distortion, then duty cycle accuracy is improved, but jitter accumulation occurs in cascaded circuits
Solution Approach 1:
The bypass duty cycle correction circuit acts as an intermediary solution that provides duty cycle correction without the jitter accumulation problem of PLL-based correction. The multiplexer serves as a mediator to selectively switch between PLL-based correction and bypass correction based on system needs
Solution Approach 2:
The system dynamically switches between two correction modes using a multiplexer. The correction approach is not fixed but adapts based on operational requirements, allowing the system to use PLL-based correction when high duty cycle accuracy is needed and bypass correction when jitter minimization is prioritized
3Adaptability or versatility
If long traces are used on PCB to connect cascaded ICs, then the system layout flexibility is improved, but RC effects cause severe duty cycle distortion
Solution Approach 1:
The duty cycle correction circuits apply preliminary anti-action by pre-correcting the distorted clock signal before it affects subsequent IC stages. The correction actively counteracts the RC effects accumulated from long PCB traces, allowing flexible layout without sacrificing signal integrity
Data Source
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AI summary
A duty cycle correction device (100) includes: a phase-locked Loop (PLL)-based duty cycle correction circuit (110), a bypass duty cycle correction circuit (120) and a multiplexer (130). The PLL-based duty cycle correction circuit (110) is configured to receive and correct an input clock signal (SPI_CLK_IN) to generate a PLL-based corrected signal (PLL_FB_CLK). The bypass duty cycle correction circuit (120) is configured to be clocked by the input clock signal (SPI_CLK_IN) to sample a logic signal at its input terminal to generate a bypass corrected signal. The multiplexer (130) is coupled to the PLL-based duty cycle correction circuit (110) and the bypass duty cycle correction circuit (120) and is configured to select one of the PLL-based corrected signal (PLL_FB_CLK), the bypass corrected signal and the input clock signal (SPI_CLK_IN) as an output clock signal (SPI_CLK_OUT).