Duty-Cycle Corrector Circuit for High-Frequency Clock Stability
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Solution Overview
Problem
Adjusting the duty-cycle of an internal clock signal with a high frequency in semiconductor devices like DRAMs is challenging, as it requires precise manipulation while maintaining the original frequency.
Innovation Solution
The implementation of a clock control circuit that generates divided clock signals and uses duty-cycle adjusters (DCAs) controlled by a DCA control circuit to adjust the duty-cycle of internal clock signals, ensuring they maintain a 50% duty-cycle while allowing for phase adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the duty-cycle of a high frequency internal clock signal is adjusted directly, then the duty-cycle precision is improved, but it becomes difficult to maintain the original frequency
Solution Approach 1:
The patent divides the high frequency internal clock signal into multiple lower frequency divided clock signals. By adjusting the duty-cycle of these divided signals at lower frequencies where adjustment is easier and more precise, then recombining them, the system achieves accurate duty-cycle control without directly manipulating the high frequency signal, thus maintaining frequency stability.
Solution Approach 2:
The patent introduces divided clock signals as intermediary elements between the internal clock signal and the duty-cycle adjustment mechanism. These intermediary signals allow duty-cycle adjustment to be performed at manageable frequency levels, and the adjusted signals serve as mediators to reconstruct the final clock signal with corrected duty-cycle while preserving the original frequency characteristics.
2Ease of operation
If divided clock signals are used to adjust duty-cycle, then the duty-cycle adjustment becomes feasible, but the device complexity increases
Solution Approach 1:
The duty-cycle adjusters are designed to handle multiple divided clock signals using the same adjustment mechanism and control logic. This multi-functional approach allows a single type of circuit block to service multiple frequency-divided signals, reducing overall complexity compared to having separate adjustment circuits for each signal.
Solution Approach 2:
The patent adjusts duty-cycle by changing temporal parameters (pulse width, timing) of the divided clock signals rather than fundamentally altering the circuit architecture. By modifying signal characteristics through controlled delay elements and timing adjustment mechanisms, the system achieves duty-cycle correction with minimal additional complexity.
Data Source
AI summary
An apparatus according to some embodiments comprises: a first clock path including a first duty-cycle adjuster that adjusts a duty cycle of a first input clock signal, a second clock path including a second duty-cycle adjuster that adjusts a duty cycle of a second input clock signal having a different phase from the first input clock signal; and a control circuit configured to detect longest one or shortest one of first, second, third, and fourth time periods to generate a control signal. The first, second, third and fourth time periods are defined by phase differences between rising edges and falling edges of the first and second input clock signals.