Duty-Cycle Corrector Using Divided Clocks for DRAM Synchronization
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Solution Overview
Problem
Adjusting the duty-cycle of high-frequency internal clock signals in semiconductor devices like DRAM while maintaining the original frequency is challenging, necessitating the use of divided clock signals to achieve accurate synchronization.
Innovation Solution
A semiconductor device configuration that includes a clock control circuit with a divider circuit generating divided clock signals, duty-cycle adjusters, and a DCA control circuit to adjust the timing of rising and falling edges of these signals, ensuring the duty-cycle is corrected to 50% by using a plurality of divided clock signals and phase splitters to generate internal clock signals with specific phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the duty-cycle of a high-frequency internal clock signal is adjusted directly, then the duty-cycle accuracy is improved, but it becomes difficult to maintain the original frequency
Solution Approach 1:
The internal clock signal is divided into multiple divided clock signals with lower frequencies. The duty-cycle correction is applied to these divided signals, and then they are combined to generate the final internal clock signal. This segmentation allows duty-cycle adjustment without directly affecting the high-frequency signal, thus maintaining both accuracy and frequency.
2Measurement precision
If multiple divided clock signals are used to adjust duty-cycle, then the duty-cycle accuracy is improved, but the device complexity increases
Solution Approach 1:
Multiple divided clock signals with corrected duty-cycles are merged together to generate the final internal clock signal. This combining approach achieves accurate duty-cycle control while using a systematic method that manages complexity through structured signal integration rather than independent adjustment circuits.
3Manufacturing precision
If the timing of rising and falling edges is adjusted independently, then the duty-cycle control precision is improved, but the control complexity increases
Solution Approach 1:
The DCA control circuit uses feedback mechanisms to independently control the timing of rising and falling edges. By monitoring the actual timing and adjusting accordingly, the system achieves precise duty-cycle control while managing complexity through automated feedback-based adjustment rather than manual configuration.
Data Source
AI summary
Disclosed herein is an apparatus that includes a clock generator configured to generate first to fourth clock signals based on an input clock signal, a first duty-cycle detector configured to output a first signal responsive to a comparison between information produced based on the first and second clock signals and based on the third and fourth clock signals, a second duty-cycle detector configured to output a second signal responsive to a comparison between information produced based on the first and fourth clock signals and based on the second and third clock signals, a third duty-cycle detector configured to output a third signal responsive to a comparison between information produced based on the first and third clock signals and based on the second and fourth clock signals, and a duty-cycle adjuster configured to adjust a duty-cycle of the input clock signal responsive to the first to third signals.