Duty Cycle Detection Circuit With Frequency-Adaptive Current Control
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Solution Overview
Problem
Existing duty cycle detection circuits in semiconductor apparatuses face challenges in accurately detecting duty cycles across varying frequencies of input clock signals, leading to potential errors and offsets due to clock skew and frequency variations.
Innovation Solution
A duty cycle detection circuit is designed with a detection block, a current amount control block, and separate rising and falling clock detection blocks, which generate and compare signals to produce a duty detection signal, while the current amount control block adjusts current paths based on the input clock frequency, minimizing duty offset and ensuring precise detection regardless of frequency variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional duty cycle detection circuit is used, then the circuit structure is simple, but the detection precision deteriorates when the input clock frequency varies
Solution Approach 1:
The patent implements dynamic current amount control by detecting the frequency of the input clock signal and adjusting the current amounts in the rising clock detection block and falling clock detection block accordingly. This dynamic adjustment compensates for frequency variations, maintaining detection precision across different operating conditions without requiring a completely redesign of the circuit structure.
Solution Approach 2:
The patent changes the current amount parameter based on the detected clock frequency. By varying the current amounts in the detection blocks as a function of frequency, the circuit maintains accurate duty cycle detection despite frequency variations, resolving the contradiction between precision and complexity.
2Stability of the object's composition
If the current amount is kept constant, then the circuit operation is simple, but the detection stability deteriorates with frequency variation
Solution Approach 1:
The patent employs feedback mechanisms where the detected clock frequency is used to adjust the current amounts in the detection blocks. This feedback loop ensures that the circuit adapts to frequency variations, maintaining stable duty cycle detection. The frequency detection result feeds back to control the current sources, creating a self-regulating system that improves stability without excessive complexity.
3Measurement precision
If separate rising and falling clock detection blocks are used, then the detection precision is improved, but the device complexity increases
Solution Approach 1:
The patent divides the duty cycle detection function into separate rising clock detection block and falling clock detection block. Each block is optimized for its specific function, allowing for more precise measurement of individual clock edges. This segmentation improves detection precision by dedicating specific circuitry to each type of clock transition, while the modular structure actually simplifies the overall design and maintenance.
Data Source
AI summary
A duty cycle detection circuit may include a detection block configured to generate a duty detection signal by detecting a duty cycle of an input clock; and a current amount control block configured to control a current flowing through the detection block in response to the input clock, regardless of a variation in a frequency of the input clock.