Programmable Duty Cycle Correction Circuit for DDR Clock Accuracy
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Solution Overview
Problem
Existing methods for precisely controlling the duty cycle of a clock signal in DDR integrated circuit memories are inefficient and costly, especially with decreasing power supply voltages affecting P-channel transistors, and require complex adjustments in manufacturing processes.
Innovation Solution
A duty cycle correcting circuit using two series-connected N-channel transistors to control the pull-up slew rate and another N-channel transistor to control the pull-down slew rate, in conjunction with dual-slope integrator circuits and input/output buffering, directly utilizing the dual-slope integrator output voltage to adjust the duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If P-channel transistors are used to control rising or falling edge slew rate, then duty cycle adjustment is achieved, but accuracy deteriorates with decreasing power supply voltages
Solution Approach 1:
The patent changes the electrical parameters of the circuit by replacing P-channel transistors with N-channel transistors for controlling slew rates. This parameter change (transistor type) maintains accurate duty cycle control even as power supply voltages decrease, since N-channel transistors are less affected by voltage drops than P-channel transistors.
2Manufacturing precision
If voltage-controlled duty cycle correcting circuitry is added to the intervening path, then duty cycle is adjusted, but device complexity increases
Solution Approach 1:
The patent merges the duty cycle correction function with the existing clock signal path by inserting control circuitry directly into the clock distribution network. The control voltage from the dual-slope integrator is combined with the clock signal path to adjust slew rates, integrating multiple functions into a unified circuit structure rather than adding separate correction stages.
Solution Approach 2:
The patent introduces a dual-slope integrator as an intermediary element that generates a control voltage based on the duty cycle error. This control voltage then mediates the adjustment of rising and falling edge slew rates through voltage-controlled transistors, providing a smooth and continuous correction mechanism that simplifies the overall control architecture.
3Ease of operation
If dual-slope integrator output voltage is translated or digitized before use, then control is achieved, but circuit complexity and voltage drops increase
Solution Approach 1:
The patent extracts the essential control function by using the dual-slope integrator output voltage directly without requiring translation or digitization circuits. The control voltage is taken directly from the integrator and applied to the voltage-controlled transistors, removing unnecessary intermediate processing stages and their associated complexity and voltage drops.
4Manufacturing precision
If P-channel to N-channel ratios are adjusted in the final driver, then duty cycle is corrected, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent implements dynamic control of the duty cycle by using voltage-controlled N-channel transistors that can adjust their conductance in real-time based on the control voltage from the dual-slope integrator. This dynamic adjustment mechanism eliminates the need for static ratio adjustments during manufacturing, allowing duty cycle correction to be achieved through electrical control rather than physical reconfiguration of transistor ratios.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides a simple and efficient method to precisely control the duty cycle of a clock signal, reducing errors and costs by using N-channel transistors and minimizing voltage drops across transistors, thereby maintaining accurate clock signal propagation.
Implementation Method 1
two dual-slope integrator circuits... When the signal has a 50% duty cycle, there will be no net charge transferred to the capacitor during a clock cycle. When the signal has a duty cycle greater than 50%, the voltage on the capacitor will increase. When the duty cycle is less than 50%, the voltage on the capacitor will decrease.
Implementation Method 2
two series-connected N-channel transistors to control the pull-up slew rate of a signal and another N-channel transistor to control the pull-down slew rate
Data Source
AI summary
A duty cycle correcting circuit for an integrated circuit memory automatically corrects the duty cycle of an input clock by measuring the relative difference between the high time and low time of the input signal and using this measurement to achieve a same-frequency, duty cycle adjusted output signal. The duty cycle correcting circuit includes a duty cycle adjust circuit that uses two series-connected N-channel transistors to control the pull-up slew rate of a signal and another N-channel transistor to control the pull-down slew rate of the same signal, two dual-slope integrator circuits, and input and output signal buffering.