Duty Cycle Regulator Using FSM Delay Sampling
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Solution Overview
Problem
Ensuring accurate duty cycle regulation of clock signals in digital circuits is challenging due to difficulties in maintaining precise timing and synchronization as process generations advance, leading to issues with transistor-level layout and formal verification, and requiring large buffering and complex digital timing paths.
Innovation Solution
A duty cycle monitoring circuit with a topological change that converts the core into standard cell logic, using a finite state machine, tunable delay circuit, and sampling circuits to achieve accurate duty cycle regulation through standard cells, enabling digital timing tools and formal verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If transistor-level layout and formal verification are used for duty cycle regulation, then measurement precision is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent replaces transistor-level mechanical layout with a behavioral model implemented in higher-level hardware description language. This substitution allows duty cycle measurement to be described functionally rather than through detailed physical transistor arrangements, reducing manufacturing complexity while preserving measurement precision through formal verification methods.
Solution Approach 2:
The patent creates a behavioral copy of the duty cycle measurement function that can be verified formally without requiring exact physical transistor-level replication. This behavioral model captures the essential measurement logic while avoiding the complexity of physical implementation details, enabling verification at an abstract level.
2Reliability
If large buffering is used for clock signals, then reliability is improved, but device area and complexity increase
Solution Approach 1:
The patent extracts the essential timing measurement function from the clock buffering system, allowing minimal buffering to be used while maintaining reliability. By separating the measurement function from the signal distribution function, the patent reduces the area required for buffering while preserving clock signal integrity through targeted measurement points.
3Measurement precision
If complex digital timing paths are used, then measurement precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent segments the timing measurement function into discrete, verifiable components that can be manufactured independently. By dividing the complex timing path into modular functional blocks with well-defined interfaces, the patent improves manufacturability while maintaining measurement precision through systematic verification of each segment.
Solution Approach 2:
The patent replaces complex physical timing paths with a behavioral model that describes timing relationships at an abstract level. This substitution simplifies manufacturing by eliminating the need for precise physical layout while preserving timing measurement precision through formal verification of the behavioral model.
Data Source
AI summary
Embodiments herein relate to a duty cycle evaluation circuit which includes a finite state machine (FSM), a logic circuit coupled to the FSM, a tunable delay circuit having an input coupled to an output of the logic circuit, a flip-flop having clock input coupled to the input of the tunable delay circuit and a data input coupled to an output of the tunable delay circuit, a first sampling circuit having a data input coupled to a data output of the flip-flop, a data output coupled to the FSM and a clock input coupled to the FSM, and a second sampling circuit having a data input coupled to the data output of the flip-flop, a data output coupled to the FSM and a clock input coupled to the FSM.