Duty Cycle Detector Self-Test Using Out-of-Range Clock Signals

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Solution Overview

Problem

Existing duty cycle detectors in modem radar applications cannot reliably self-test their functionality, leading to potential undetected errors in clock signals, which can result in degraded system performance and misinterpreted data.

Innovation Solution

A circuit and method that generate a signal with a deliberately out-of-specification duty cycle to test the duty cycle detector, allowing for the detection of errors and generation of a flag if the detector is not functioning correctly, thereby ensuring accurate operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a duty cycle detector is used to monitor clock signals in radar applications, then system reliability is improved, but the ability to self-test the detector's functionality is insufficient

Engineering Contradiction:
Improvedetector functionalityVSAvoidself-testing capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The duty cycle detector is equipped with self-testing capability that allows it to automatically test its own functionality without requiring external test equipment. The detector generates test signals internally and evaluates its own response, enabling autonomous verification of its operational status and accuracy.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The self-test function performs preliminary verification of the detector's functionality before actual radar operation begins. By testing the detector's response to known test signals with predetermined duty cycles, the system ensures the detector is functioning correctly before monitoring critical clock signals, preventing undetected errors during operation.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If the duty cycle detector operates without self-testing, then device complexity is reduced, but measurement precision of detector functionality cannot be verified

Engineering Contradiction:
Improvedetector structureVSAvoiddetector accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The self-test mechanism creates a copy of the normal operation path by routing test signals through the same detection circuitry used for actual clock signals. This allows verification of detector accuracy without adding significant structural complexity, as the test path mirrors the operational path rather than requiring separate test hardware.

Inventive Principle:
Principle #26Copying

3Measurement precision

If signals with out-of-specification duty cycles are used for testing, then detector accuracy is verified, but system operation may be interrupted

Engineering Contradiction:
Improvedetector accuracy verificationVSAvoidsystem operational continuity
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The self-test function operates periodically rather than continuously, performing accuracy verification at designated intervals or at system startup. This periodic testing allows the detector to be challenged with out-of-specification duty cycle signals to verify accuracy, while maintaining normal radar operation during non-test periods, thus balancing verification needs with operational continuity.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentEP3923005B1Duty cycle detector self-testing
Publication Date: 2024.08.07 NXP USA INC
  • EP3923005B1 patent drawingFigure 1~2
  • EP3923005B1 patent drawingFigure 3a~3b
  • EP3923005B1 patent drawingFigure 4

AI summary

The disclosure relates to apparatus and methods for self-testing of a duty cycle detector. Example embodiments include a circuit (201) comprising: a clock signal generator (205) configured to provide an output clock signal (203) having a duty cycle; a duty cycle detector (208) arranged to receive the output clock signal (203) and provide an output flag if the duty cycle of the clock signal (203) is outside a predetermined range; a controller (214) arranged to provide a duty cycle select signal (216) to the clock signal generator (205) to cause the clock signal (203) to have a duty cycle outside the predetermined range and to receive the output flag to confirm operation of the duty cycle detector (208).