Duty Cycle Corrector Using Differential Clock Signal Comparison
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Solution Overview
Problem
Maintaining a duty cycle of 50% in high-speed systems or devices is challenging due to variations in manufacturing process, supply voltage, and operating temperature, which affect the equal durations of high and low states in clock signals.
Innovation Solution
Employing a single-to-differential converter that transforms a single-ended input signal into complementary output signals using a duty cycle corrector, which includes a duty cycle altering circuit, differential signal generator, filter circuit, and comparator to ensure a duty cycle of substantially 50%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single-ended input signal is used in high-speed systems, then the system operation is simplified, but the duty cycle cannot be maintained at 50% due to variations in manufacturing process, supply voltage, and operating temperature
Solution Approach 1:
The patent introduces a duty cycle corrector as an intermediary component between the single-ended input signal and the output clock signal. This corrector includes a differential signal generator that converts the single-ended signal into differential signals, and a duty cycle altering circuit that adjusts the duty cycle based on these differential signals, thereby maintaining 50% duty cycle despite process, voltage, and temperature variations
Solution Approach 2:
The patent replaces the conventional single-ended signal processing mechanism with a differential signal processing mechanism. By using differential signals and a duty cycle corrector circuit, the system achieves automatic duty cycle correction without requiring manual adjustment or complex calibration, substituting the simple but inaccurate single-ended path with a more complex but self-correcting differential path
2Manufacturing precision
If duty cycle correction circuits are added to maintain 50% duty cycle, then the duty cycle accuracy is improved, but the device complexity increases
Solution Approach 1:
The patent employs dynamic elements in the duty cycle corrector, including differential signal generation and switching circuits that automatically adjust the duty cycle in real-time. The circuit responds dynamically to variations in process, voltage, and temperature conditions, maintaining 50% duty cycle through active correction rather than static design
Solution Approach 2:
The patent changes the signal representation from single-ended to differential mode within the duty cycle corrector. This parameter change enables the circuit to exploit the symmetry of differential signals for automatic duty cycle correction, transforming the problem from one requiring complex absolute timing control to one utilizing differential balance
Data Source
AI summary
A device includes a clock signal generator and a transmitter circuit. The clock signal generator receives a first input clock signal, generates an output clock signal, and includes a phase generator and a duty cycle corrector. The phase generator generates a plurality of second input clock signals from the input clock signal. The duty cycle corrector adjusts a duty cycle of the second input clock signal with reference to a control signal, generates a single-ended input signal and complementary output signals from the single-ended input signal, compares the complementary output signals, and generates a result of comparison that serves as the control signal. The transmitter circuit receives an input data signal, processes the input data signal in response to the output clock signal, generates an output data signal, and transmits the output data signal.