Duty Cycle Correction Circuit for Single-Line DLL Clock Transmission
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Solution Overview
Problem
Conventional semiconductor integrated circuits face inefficiencies due to signal distortion and increased area and power consumption caused by the need for a pair of clock signal transmission lines to correct duty cycles, which complicates duty ratio maintenance and reduces operation efficiency.
Innovation Solution
A duty cycle correction apparatus that includes a fixed delay unit, a variable delay unit, a duty cycle correction unit, and a delay control unit to generate and correct clock signals, allowing for improved duty ratio characteristics without requiring the duty cycle correction apparatus to be within the DLL circuit, thus reducing signal distortion and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a duty cycle correction apparatus is provided in the DLL circuit with a pair of transmission lines, then the duty cycle of clock signals can be corrected, but signal distortion occurs and area and power utilization efficiency deteriorate
Solution Approach 1:
The duty cycle correction apparatus is extracted from the DLL circuit and placed in the data output apparatus. This separation removes the harmful effect of signal distortion caused by the DLL circuit's transmission lines while preserving the duty cycle correction function. The correction apparatus now operates on clock signals after they have been transmitted, avoiding the distortion problem at its source.
Solution Approach 2:
A single transmission line is used as an intermediary to transmit only one clock signal from the DLL circuit to the data output apparatus. This eliminates the need for a pair of transmission lines and their associated distortion problems, while the duty cycle correction apparatus compensates for any duty cycle issues that may arise during transmission.
2Manufacturing precision
If a pair of transmission lines is used to transmit clock signals for duty cycle correction, then the duty cycle can be maintained, but area and power utilization efficiency deteriorate
Solution Approach 1:
The duty cycle correction function is extracted from the transmission line structure and implemented as a separate apparatus in the data output apparatus. This allows a single transmission line to be used instead of a pair, reducing the area occupied by transmission lines while the correction apparatus maintains the required duty cycle precision.
Solution Approach 2:
The single transmission line serves the universal function of transmitting clock signals without requiring dedicated paired lines for differential signaling. The duty cycle correction apparatus provides the additional functionality needed to maintain signal integrity, combining the roles of transmission and correction in a more area-efficient manner.
3Manufacturing precision
If a pair of transmission lines is used for clock signal transmission, then duty cycle correction is achieved, but power consumption increases
Solution Approach 1:
The duty cycle correction apparatus is extracted from the transmission line system and placed in the data output apparatus. This allows the use of a single transmission line instead of a pair, reducing the power consumption associated with transmitting multiple clock signals, while the correction apparatus ensures duty cycle accuracy is maintained.
4Manufacturing precision
If the duty cycle correction apparatus is placed in the DLL circuit, then correction can be performed early, but operation efficiency deteriorates due to increased complexity
Solution Approach 1:
The duty cycle correction apparatus is extracted from the DLL circuit and relocated to the data output apparatus. This separation improves operation efficiency by allowing the DLL circuit to focus on its primary function of generating clock signals with correct phase relationships, while the correction apparatus handles duty cycle adjustments without adding complexity to the DLL circuit's operation.
Data Source
AI summary
A duty cycle correction apparatus includes a fixed delay unit configured to set a fixed delay time to a DLL clock signal and generate a delay rising clock signal; a variable delay unit configured to delay the DLL clock signal in response to a control signal and generate a delay falling clock signal; a duty cycle correction unit configured to generate a correction rising clock signal and a correction falling clock signal that are toggled in conformity with edge timing of the delay rising clock signal and the delay falling clock signal; and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal and generate the control signal.