Duty-Cycle Corrector Circuit Using DLL and Digital Error Detection
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Solution Overview
Problem
Existing duty-cycle corrector circuits for high-speed circuits face challenges in accurately correcting duty-cycle errors due to variations in process, voltage, and temperature (PVT), and they often require complex circuits and high power consumption.
Innovation Solution
The proposed solution involves a duty-cycle corrector circuit that utilizes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit adjusts the delay between local clock signals to align their rising edges, while the DCC circuit adjusts the duty cycles of these signals to achieve a fifty percent duty cycle, using a duty adjusting (DA) circuit and a pulse generator (PG) circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an analog integrator is used to detect duty cycle error, then the circuit can detect duty cycle variations, but it can only be used in low-speed applications
Solution Approach 1:
The patent replaces the analog integrator (mechanical/electrical continuous system) with a digital duty-cycle corrector circuit that uses digital logic elements (D flip-flops, XOR gates, counters) to detect and correct duty cycle errors. This substitution enables the circuit to operate at high speeds while maintaining accurate duty cycle detection through digital sampling and counting mechanisms.
2Measurement precision
If two delay lines are used to correct duty cycle accuracy, then the duty cycle can be corrected, but the circuit becomes complicated and power consumption increases
Solution Approach 1:
The patent segments the duty cycle correction function into distinct digital modules: a first D flip-flop for sampling the input clock, a second D flip-flop for generating the inverted clock signal, an XOR gate for detecting duty cycle errors, and a counter for measuring the error duration. This segmentation allows each component to perform a specific function with simple logic, reducing overall circuit complexity while achieving accurate duty cycle correction.
3Measurement precision
If two delay lines are used to correct duty cycle accuracy, then the duty cycle can be corrected, but power consumption becomes relatively high
Solution Approach 1:
The patent employs simple digital logic elements (D flip-flops, XOR gates, counters) that consume minimal power compared to complex analog circuits or multiple delay lines. These digital components operate with low power consumption while providing accurate duty cycle correction through discrete sampling and counting operations, effectively replacing high-power consumption elements with low-power digital alternatives.
4Measurement precision
If a comparator circuit is used to compare signal levels of two delay lines, then duty cycle correction can be performed, but the comparator circuit is complex and consumes large die area
Solution Approach 1:
The patent extracts the duty cycle error detection function from a complex comparator circuit and implements it using simple digital logic: an XOR gate that compares the input clock signal with the inverted clock signal. This extraction eliminates the need for a large-scale comparator circuit, reducing die area while maintaining the ability to detect duty cycle errors through the XOR output pulse width.
Data Source
AI summary
A duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. The DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. The DCC circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. The duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.