Dual-Edge Duty Cycle Correction for Faster Clock Locking
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Solution Overview
Problem
Conventional duty cycle correction systems, such as delay lock loops, face limitations in achieving fast and accurate control over the duty cycle of clock signals, particularly in high-speed data transfers, due to the need for phase detection only once per signal period and the lack of synchronization between the rising and falling edges of the clock signals.
Innovation Solution
A duty cycle correction system that includes a duty cycle adjustor and phase detectors to align the transitions of the clock signal and its inverted version, allowing for precise adjustment of the duty cycle by delaying either the rising or falling edge of the input clock signal, ensuring a 50% duty cycle through iterative comparison and adjustment processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If phase detection is performed only once per signal period in conventional DLLs, then the system structure remains simple, but the locking time becomes excessively long
Solution Approach 1:
The phase detection function is segmented into two separate phase detectors: one detects the rising edge phase error, and the other detects the falling edge phase error. This segmentation allows simultaneous phase detection at both edges of the clock signal, enabling faster locking without requiring a single complex phase detector that would need to process both edges sequentially.
Solution Approach 2:
The system performs phase detection periodically at both rising and falling edges of the clock signal simultaneously. By utilizing both edges for phase detection, the locking process occurs twice per signal period compared to conventional single-edge detection, significantly reducing the time required to achieve lock.
2Measurement precision
If the rising edge of Clk 180 Out is not locked to the falling edge of ClkIn, then the delay line delays can differ, but this causes duty cycle deviation from 180 degrees
Solution Approach 1:
The system employs feedback control through two phase detectors that continuously monitor the phase relationship between the clock signal edges and the delayed signal edges. The phase error signals from both detectors are fed back to adjust the delay lines, ensuring that the rising edge of Clk 180 Out remains locked to the falling edge of ClkIn, thereby maintaining precise 180-degree duty cycle accuracy.
Solution Approach 2:
The system uses asymmetric control of the two delay lines (delay line 14 for rising edge, delay line 16 for falling edge) through separate phase detectors. This asymmetric approach allows independent adjustment of each delay line to compensate for process variations and ensure precise edge alignment, achieving accurate duty cycle control.
3Loss of time
If a single phase detector is used to determine phase error once per period, then the device complexity is low, but the locking time becomes excessively long
Solution Approach 1:
The phase detection task is divided into two separate phase detectors operating in parallel: one dedicated to rising edge detection and another to falling edge detection. This segmentation enables simultaneous phase error measurement at both edges, reducing the overall locking time without requiring a single complex phase detector.
Solution Approach 2:
The system maintains continuous phase detection at both rising and falling edges throughout operation. This continuous dual-edge detection ensures that phase errors are constantly corrected, achieving fast locking and maintaining synchronization, unlike conventional systems that perform detection only once per period.
Data Source
AI summary
Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.