Duty Cycle Correction Circuit for Dual-Phase Clock Stability
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Solution Overview
Problem
Existing duty cycle correction circuits in semiconductor devices are large, complex, and consume high current, making it difficult to achieve a stable 50:50 duty cycle ratio essential for precise clock operations, particularly in image sensing devices using a double data rate scheme.
Innovation Solution
A duty cycle correction circuit that includes inversion blocks and phase correction units to generate corrected clocks for both the original and phase-shifted clocks, ensuring accurate duty cycle correction based on logic states and phase relationships, thereby minimizing circuit area and current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a duty cycle correction circuit is implemented to correct clock duty cycles to 50:50 ratio, then the operation stability and performance of the semiconductor device is improved, but the circuit area, structural complexity, and current consumption increase significantly
Solution Approach 1:
The patent combines the duty cycle correction functionality for two phase-shifted clocks into a single integrated correction circuit. The correction unit simultaneously processes both clocks by generating inverted versions of each clock and using logic operations on all four signals (original and inverted for both clocks) to produce corrected output clocks, thereby reducing overall circuit complexity while maintaining correction effectiveness
Solution Approach 2:
The correction circuit is designed to handle multiple clock signals with different phase relationships using a universal correction mechanism. The same correction unit processes both the first clock and second clock (which are phase-shifted by approximately 180 degrees) through identical logic operations, making the circuit multi-functional and reducing the need for separate correction circuits for each clock
2Manufacturing precision
If existing duty cycle correction circuits are used to ensure precise 50:50 duty cycle ratio, then valid window regions of signals and data are secured, but the circuit area and current consumption become excessively large
Solution Approach 1:
The correction circuit is segmented into functional blocks: inversion units that generate inverted clock signals, and a correction unit that performs logic operations. This segmentation allows each block to be optimized independently and reduces the overall area by eliminating redundant components while maintaining precise duty cycle correction capability
Solution Approach 2:
The patent changes the operational parameters of the correction circuit by using logic operations on inverted and non-inverted clock signals simultaneously. This parameter change approach allows the circuit to achieve precise 50:50 duty cycle correction with reduced transistor count and smaller circuit area compared to traditional correction methods
3Reliability
If traditional duty cycle correction circuits are implemented to correct clocks from PLL or VCO, then stable circuit operations are achieved, but the current consumption becomes unacceptably high
Solution Approach 1:
The correction circuit operates periodically in sync with the input clock signals, using the inherent periodicity of the clocks to be corrected. The inversion units and logic operations are triggered by the clock edges themselves, eliminating the need for continuous high-current operation and reducing average current consumption while maintaining stable correction
Data Source
AI summary
A duty cycle correction circuit includes an inversion block suitable for generating a first inverted clock that is in an inversion relationship with a first clock and a second inverted clock that is in an inversion relationship with a second clock, in response to the first clock and the second clock, and a correction block suitable for generating a first corrected clock having a corrected duty cycle relative to the first clock and a second corrected clock having a corrected duty cycle relative to the second clock, based on a logic state of the first clock, a logic state of the second clock, a logic state of the first inverted clock, and a logic state of the second inverted clock.