Duty Cycle Corrector with Edge Modulation Beyond Interpolator Range
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Solution Overview
Problem
Duty cycle correctors using the open-loop mode face challenges in reliability and speed due to limitations in clock interpolating range, leading to incomplete duty cycle correction.
Innovation Solution
A duty cycle corrector is designed with a delay chain, edge detector, falling edge shift controller, and multiple falling edge modulator cores to generate sampling signals, determine modulation direction and width, and perform phase interpolation, enabling duty cycle correction even when the clock is out of the interpolating range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a duty cycle corrector uses a closed-loop mode with feedback signal, then reliability of duty cycle correction is improved, but speed of duty cycle correction decreases due to delay to stabilize feedback circuit
Solution Approach 1:
The patent divides the duty cycle correction function into two independent parallel paths: a closed-loop path for reliability and an open-loop path for speed. The closed-loop corrector handles precision correction with feedback, while the open-loop corrector provides rapid initial correction, allowing both reliability and speed requirements to be satisfied simultaneously through functional segmentation.
2Speed
If a duty cycle corrector uses an open-loop mode with phase interpolator, then speed of duty cycle correction is improved, but reliability decreases and correction fails when clock is out of interpolating range
Solution Approach 1:
The open-loop corrector performs preliminary duty cycle correction at high speed before the closed-loop corrector takes over for final precision adjustment. This preliminary action allows the system to quickly bring the duty cycle within the interpolating range, after which the closed-loop mechanism ensures accurate final correction, thus maintaining both speed and reliability.
3Speed
If a phase interpolator is used in open-loop mode, then speed is improved, but duty cycle correction fails when clock is out of interpolating range due to improper interpolating
Solution Approach 1:
The patent introduces a range detector as an intermediary component that monitors whether the clock signal is within the interpolating range. When the signal is out of range, the range detector activates the closed-loop corrector to first bring the signal within the acceptable range, enabling the phase interpolator to function properly. This intermediary mechanism ensures the system can handle both in-range and out-of-range conditions reliably.
Data Source
AI summary
A duty cycle corrector includes a delay chain, an edge detector, a falling edge shift (FES) controller, a plurality of falling edge modulator (FEM) cores, and a phase interpolator. The delay chain delays a first clock to generate a delay clock, and generates first and second sampling control signals. The edge detector samples the first clock and a second clock using the first and second sampling control signals to obtain first and second sampling signals. The FES controller determines a modulation direction and a modulation width based on the first and second sampling signals. The plurality of FEM cores first modulate the first edge of the first clock and second modulate the first edge of the delay clock using the modulation direction and the modulation width. The phase interpolator performs phase interpolation on the results of the first and second modulations.