Duty Cycle Clock Loop With Fast Locking and Low Jitter
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Solution Overview
Problem
Existing duty cycle adjustment apparatuses in high-precision and high-speed integrated circuit systems face challenges in achieving simple circuit implementation, proper power consumption, and minimal area usage while maintaining fast locking speed, with existing methods either increasing complexity and power consumption or limiting locking speed improvement.
Innovation Solution
A duty cycle adjustment apparatus comprising a first edge extraction unit, locking discrimination unit, integration unit, charge pump, second edge extraction unit, and phase discriminator, which uses a closed-loop RC integrator structure to maintain a constant slope control signal and reduce locking time by 30% to 60% compared to conventional methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a multistage driven loop gain is added to achieve fast locking, then locking speed is improved, but clock jitter increases and system performance is restricted
Solution Approach 1:
The patent segments the feedback signal into two paths: a main feedback path using the output clock signal for stable operation, and a auxiliary path using the input clock signal for fast locking. The locking discrimination unit selectively activates these paths based on locking state, allowing fast acquisition without excessive loop gain that would cause jitter.
Solution Approach 2:
The system dynamically switches between different feedback modes: during acquisition phase, the input clock is fed back for fast locking; during locked phase, the output clock is fed back for stable operation. This dynamic adaptation allows the system to achieve fast locking without the clock jitter that would result from continuously high loop gain.
2Speed
If a converter module and switched charge pump are added for fast locking, then locking speed is improved, but circuit complexity and area increase
Solution Approach 1:
The patent makes the existing charge pump serve dual purposes: it generates the output clock signal and simultaneously provides the feedback mechanism for fast locking. The locking discrimination unit utilizes existing circuit nodes (input clock and output clock) without requiring additional converter modules, allowing the system to self-achieve fast locking functionality.
Solution Approach 2:
The charge pump is designed to perform multiple functions: generating the output clock signal with adjustable duty cycle and providing the feedback signal for locking detection. By making the feedback mechanism utilize existing circuit elements rather than adding dedicated fast-locking hardware, the patent achieves multi-functionality without increasing circuit complexity.
3Loss of time
If a second order filter is used to convert the loop system order, then locking time is improved, but area and power consumption increase
Solution Approach 1:
The patent changes the operational parameters of the existing first-order loop by dynamically switching feedback sources rather than increasing system order. By using the input clock as feedback during acquisition, the system achieves fast locking through parameter optimization rather than adding filter stages, avoiding the area and power penalties of second-order filters.
Data Source
AI summary
A duty cycle adjustment apparatus comprises a first edge extraction unit for extracting a rising edge of a first clock signal; a locking discrimination unit configured to output a control signal according to a comparison result between a discrimination voltage and a stabilized voltage, and select to connect the first clock signal or the clock output signal; an integration unit, configured to convert the feedback signal into the stabilized voltage, amplify the stabilized voltage to reach a reference voltage, and output a control voltage; a charge pump, configured to output a second clock signal according to the control voltage; a second edge extraction unit, configured to extract a falling edge of the second clock signal; and a phase discriminator, configured to compare a phase of the rising edge of the first clock signal with a phase of the falling edge of the second clock signal to generate the clock output signal.