Duty Cycle Correction Circuit With Feedback Delay Control
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Solution Overview
Problem
Modern high-speed large-scale integrated circuits face challenges in stabilizing the duty cycle of clock signals around 50%, which affects performance, particularly in RF and communication fields where precise duty cycles are required for optimal operation.
Innovation Solution
A duty cycle correction circuit comprising a signal adjustment circuit, duty cycle detection circuit, and digital control delay circuit, which work together to detect and adjust the duty cycle of clock signals to achieve a high-precision 50% duty cycle by performing delay operations based on feedback results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed capacitance is used in the duty cycle detection circuit, then the circuit design is simple, but different process corner parameters cause different charging and discharging speeds leading to duty cycle deviation
Solution Approach 1:
The patent replaces fixed capacitance with dynamically adjustable capacitance values. The duty cycle detection circuit uses multiple capacitance elements (first capacitance, second capacitance, third capacitance, fourth capacitance) that can be selectively connected based on feedback, allowing the capacitance to adapt to different process corner parameters and maintain accurate duty cycle detection across varying conditions.
Solution Approach 2:
The patent changes the capacitance parameter dynamically based on detected duty cycle values. When the duty cycle deviates from 50%, the circuit switches between different capacitance values (e.g., using first and second capacitance for duty cycle < 50%, third and fourth capacitance for duty cycle > 50%) to correct the charging and discharging speeds, thereby maintaining manufacturing precision across process variations.
2Measurement precision
If the capacitance elements discharge too early or too late, then the duty cycle detection becomes inaccurate, but adjusting capacitance values increases circuit complexity
Solution Approach 1:
The patent implements a feedback mechanism where the duty cycle detection circuit continuously monitors the duty cycle of the input signal and generates feedback control signals. Based on this feedback, the circuit determines whether to switch between different capacitance configurations, creating a closed-loop system that automatically maintains accurate duty cycle detection without manual intervention.
Solution Approach 2:
The circuit performs self-adjustment by automatically selecting appropriate capacitance values based on its own duty cycle measurements. The duty cycle detection circuit monitors its own performance and triggers capacitance switching when deviation is detected, enabling the system to self-correct without external control, thereby reducing overall system complexity while maintaining precision.
3Measurement precision
If phase-locked loop output is used to ensure frequency accuracy, then frequency precision is improved, but duty cycle stability around 50% becomes difficult to maintain
Solution Approach 1:
The patent separates the frequency control function (handled by the phase-locked loop) from the duty cycle control function (handled by the duty cycle correction circuit). This segmentation allows each subsystem to optimize its specific function: the PLL maintains frequency accuracy while the duty cycle correction circuit independently adjusts duty cycle stability through selective capacitance switching, resolving the conflict between the two requirements.
Data Source
AI summary
The present application discloses a duty cycle correction circuit. The duty cycle correction circuit includes signal input terminal; a signal adjustment circuit electrically connected to the signal input terminal and configured to receive a first clock signal and convert the first clock signal into a second clock signal; a duty cycle detection circuit electrically connected to the signal adjustment circuit and configured to detect a duty cycle of the second clock signal and generate a feedback result; and a digital control delay circuit electrically connected to the duty cycle detection circuit, the signal adjustment circuit and the signal input terminal, respectively. The digital control delay circuit is configured to, according to the feedback result, perform a corresponding delay operation on the second clock signal generated by the signal adjustment circuit.