Duty Cycle Corrector With Feedback-Stretched Clock Pulses
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In synchronous digital systems, clock signals often do not have the desired 50% duty cycle, leading to issues with component synchronization and phase uncertainty, particularly when correcting duty cycles greater than or less than 50%.
Innovation Solution
A duty cycle corrector circuit that generates an output clock signal with a desired 50% duty cycle by delaying either rising or falling edges of the input clock signal, using a pulse generating stage and a feedback loop to control the delay, ensuring the output clock signal has a fixed and independent phase relative to the input.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If duty cycle correction is performed by delaying edges of the clock signal, then the desired 50% duty cycle is achieved, but phase uncertainty increases and synchronization reliability deteriorates
Solution Approach 1:
Instead of delaying edges of the input clock signal to correct duty cycle, the invention inverts the approach by generating a new clock signal with precise 50% duty cycle through edge detection and controlled pulse generation. The rising and falling edges are detected and used to trigger complementary pulses that guarantee exact 50% duty cycle, eliminating phase uncertainty associated with delay-based methods.
Solution Approach 2:
The invention employs feedback mechanisms where the detected edges of the input clock signal are used to control the generation of output pulses. The rising edge detection triggers a high pulse, and the falling edge detection triggers a low pulse, creating a closed-loop system that automatically adjusts the output duty cycle to match the desired 50% regardless of input variations.
2Manufacturing precision
If duty cycle correction is performed by delaying edges, then the desired duty cycle is achieved, but the delay becomes dependent on input duty cycle causing phase uncertainty
Solution Approach 1:
The invention performs preliminary edge detection and triggers pulse generation in advance of any potential duty cycle deviation. By detecting rising and falling edges immediately and generating corresponding output pulses based on these detections, the system eliminates the need for variable delays that would otherwise be required to correct duty cycle, thus preventing phase uncertainty from occurring in the first place.
Solution Approach 2:
The invention changes the fundamental parameter approach from using variable time delays (which depend on input duty cycle) to using fixed-duration pulses triggered by edge detection. This parameter transformation converts the duty cycle correction problem from a time-delay adjustment into a pulse-width control problem, where the pulse width is predetermined and independent of input signal characteristics.
3Device complexity
If a simple delay method is used to correct duty cycle, then the circuit complexity is reduced, but the adaptability to different duty cycle inputs deteriorates
Solution Approach 1:
The invention creates a universal duty cycle corrector that can handle any input duty cycle (20%, 30%, 70%, 80%, or any other value) through a single standardized circuit architecture. The edge detection mechanism and pulse generation system work identically regardless of the input duty cycle, making the circuit universally adaptable without requiring redesign or adjustment for different input conditions.
Solution Approach 2:
The feedback mechanism continuously monitors the input clock signal edges and automatically adjusts the output pulse timing and width to maintain 50% duty cycle. This closed-loop operation enables the circuit to adapt to any input duty cycle variation automatically, providing versatility without increasing complexity, as the same feedback-controlled pulse generation handles all input scenarios.
Data Source
AI summary
The invention relates to a duty cycle corrector for generating from an input clock signal an output clock signal having a desired duty cycle. The duty cycle corrector comprises a pulse generating stage for generating from the input clock signal a pulsed clock signal. The pulse generating stage converts rising edges of the input clock signal into pulses, each of which pulses is shorter than the desired duty cycle times the clock period. The duty cycle corrector further comprises a pulse stretching stage for generating from the pulsed clock signal the output clock signal, the pulse stretching stage delaying falling edges of the pulsed clock signal by a controlled delay. The duty cycle corrector may comprise a duty cycle detector for generating a control signal as a function of the duty cycle of the output clock signal, and a feedback path for delivering the control signal to the pulse stretching stage so as to increase the controlled delay when the duty cycle is less than the desired duty cycle and to decrease the controlled delay when the duty cycle is greater than the desired duty cycle. The invention also relates to a method of generating from an input clock signal an output clock signal having a desired duty cycle.