Duty Cycle Correction Circuit With Flip-Flop Edge Detection
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Solution Overview
Problem
Conventional duty ratio correction circuits in semiconductor memory devices face challenges due to large area occupation and high power consumption by inverters, and are sensitive to process, voltage, and temperature variations, leading to instability and increased production costs.
Innovation Solution
A duty ratio correction circuit utilizing a flip-flop circuit with a first and second internal clock generator, where the output node is precharged by a power supply voltage in response to a clock signal and a reset signal, generating internal clock signals with a desired duty ratio without the need for weight control, thereby reducing the number of inverters and improving stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional duty ratio correction circuits use multiple inverters for weighting clock signals, then duty ratio correction is achieved, but area occupation and power consumption increase
Solution Approach 1:
The patent changes the fundamental operating parameters of the duty ratio correction circuit by replacing inverter-based weighting with flip-flop-based edge detection. This parameter change transforms the circuit from using multiple parallel inverters to using sequential flip-flop elements triggered by clock edges, thereby reducing area while maintaining correction functionality
Solution Approach 2:
The patent extracts and removes the inverter weighting units from the duty ratio correction circuit. By eliminating the multiple inverters required for signal weighting and instead using flip-flops to detect rising and falling edges, the circuit achieves duty ratio correction with significantly reduced area occupation
2Reliability
If conventional duty ratio correction circuits use multiple inverters for weighting clock signals, then duty ratio correction is achieved, but power consumption increases
Solution Approach 1:
The patent changes the operational mode from continuous inverter operation to event-driven flip-flop operation. The flip-flops are only activated on clock edges (rising or falling), reducing the average power consumption compared to multiple inverters that continuously process and weight the clock signals
Solution Approach 2:
The patent implements periodic action by using flip-flops that are triggered only at specific moments (clock edges) rather than continuous operation. The first flip-flop is triggered on rising edges and the second on falling edges, creating a periodic, event-driven operation pattern that reduces overall power consumption
3Reliability
If conventional duty ratio correction circuits use inverter weighting, then duty ratio can be corrected, but the circuit becomes sensitive to PVT variations
Solution Approach 1:
The patent implements self-service by using the clock signal itself to trigger the flip-flops. The rising edge of the clock automatically triggers the first flip-flop, and the falling edge automatically triggers the second flip-flop, eliminating the need for external weighting control signals that are sensitive to PVT variations
Solution Approach 2:
The patent uses feedback mechanisms where the output of each flip-flop is fed back to control subsequent operations. The first flip-flop output feeds back to control the precharge timing, and the second flip-flop output feeds back to control the duty ratio adjustment, creating a self-regulating system that compensates for PVT variations
4Reliability
If conventional duty ratio correction circuits are used, then duty ratio correction is possible, but mask revisions are required increasing production costs
Solution Approach 1:
The patent employs a design that is inherently adaptable to process variations without requiring expensive mask revisions. The flip-flop-based architecture with edge-triggered operation provides robust duty ratio correction that works across process variations, eliminating the need for costly post-fabrication mask revisions
Data Source
AI summary
A duty ratio correction circuit includes a duty cycle ratio controlling unit configured to generate an internal clock signal having a duty cycle ratio defined according to a first reference clock signal and a reset signal and a reset signal generating unit configured to generate the reset signal in response to a second reference clock signal and the internal clock signal fed back thereto.