Duty-Cycle-Corrected Frequency Divider for 50% DDR Clocking
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Solution Overview
Problem
In digital circuit systems, frequency dividers struggle to produce a clock signal with a duty cycle of 50%, which is crucial for preventing timing issues, especially in Double Data Rate (DDR) systems where both rising and falling edges must be sampled simultaneously.
Innovation Solution
A frequency divider incorporating a duty cycle correction circuit that performs P-frequency multiplication and Q-frequency division operations on a clock signal to achieve a third processed signal with a duty cycle of 50%, utilizing a combination of XOR and delay sub-circuits for frequency multiplication and edge-triggered D flip-flops for division.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional frequency divider is used to divide clock signal frequency, then the frequency division function is achieved, but the output duty cycle cannot be maintained at 50%
Solution Approach 1:
The frequency divider is segmented into three functional modules: a first frequency dividing circuit for initial frequency division, a duty cycle correction circuit for adjusting the duty cycle back to 50%, and a second frequency dividing circuit for final frequency division. This segmentation allows each module to perform its specific function independently, ensuring the output signal maintains a 50% duty cycle while achieving the desired frequency division ratio.
Solution Approach 2:
The duty cycle correction circuit performs preliminary action by correcting the duty cycle of the intermediate signal before it enters the second frequency dividing circuit. This preliminary correction ensures that the final output signal from the second frequency divider maintains a 50% duty cycle, preventing duty cycle distortion from propagating through the remaining circuit stages.
2Reliability
If frequency division is performed without duty cycle correction, then the circuit complexity is reduced, but timing issues occur in DDR systems
Solution Approach 1:
The frequency divider is segmented into three functional modules: a first frequency dividing circuit for initial frequency division, a duty cycle correction circuit for adjusting the duty cycle back to 50%, and a second frequency dividing circuit for final frequency division. This segmentation allows each module to perform its specific function independently, ensuring the output signal maintains a 50% duty cycle while achieving the desired frequency division ratio.
Solution Approach 2:
The duty cycle correction circuit performs preliminary action by correcting the duty cycle of the intermediate signal before it enters the second frequency dividing circuit. This preliminary correction ensures that the final output signal from the second frequency divider maintains a 50% duty cycle, preventing duty cycle distortion from propagating through the remaining circuit stages.
Data Source
AI summary
At least one embodiment of the present disclosure provides a frequency divider, an electronic device and a frequency dividing method. The frequency divider includes a duty cycle correction circuit and a frequency divider circuit. The duty cycle correction circuit is configured to receive a first clock signal, and perform a first processing on the first clock signal to generate a first processed signal. The frequency dividing circuit is configured to receive the first processed signal, and perform a second processing on the first processed signal to generate a second processed signal. The duty cycle correction circuit is further configured to receive the second processed signal, and perform a third processing on the second processed signal to generate a third processed signal. The frequency divider can correct the duty cycle of the output clock signal while dividing the frequency.