Duty Cycle Calibration Circuit for Low-Jitter Frequency Doubling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Cascaded PLL circuits in semiconductor applications experience unqualified jitter and increased power consumption due to dedicated power supplies and bumps, limiting their performance and efficiency.
Innovation Solution
A circuit and method utilizing a duty cycle calibration device, phase adjusting device, and duty cycle measurement device to adjust the duty cycle of input signals, employing all-digital design without dedicated power supplies or power bumps, thereby reducing power consumption and improving jitter and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cascaded PLL circuits are used to increase frequency, then frequency multiplication is achieved, but jitter increases and power consumption increases due to dedicated power supplies and bumps
Solution Approach 1:
The patent segments the frequency multiplication function into multiple duty cycle calibration stages (e.g., 2x, 4x, 8x multipliers) that can be cascaded. Each stage independently calibrates its output duty cycle to 50%, preventing jitter accumulation that would occur in conventional cascaded PLL circuits. This segmentation allows frequency multiplication while maintaining signal quality.
Solution Approach 2:
The patent changes the duty cycle parameter of the input signal through calibrated adjustment to achieve frequency multiplication. By precisely controlling and adjusting the duty cycle parameter (e.g., transforming non-50% duty cycle signals into 50% duty cycle signals), the system achieves frequency multiplication without the jitter problems of conventional PLL approaches.
2Speed
If cascaded PLL circuits with dedicated power supplies are used, then frequency multiplication is achieved, but power consumption increases
Solution Approach 1:
The patent creates a universal duty cycle calibration circuit that can function as both a duty cycle corrector and a frequency multiplier. This multi-functional approach eliminates the need for separate dedicated power supplies and control circuits for each PLL stage, thereby reducing overall power consumption while achieving the same frequency multiplication effect.
Solution Approach 2:
The patent extracts and removes the dedicated power supply and control circuitry components from the frequency multiplication system. By using the duty cycle calibration circuit to perform frequency multiplication instead of conventional PLL circuits, the system eliminates unnecessary power-consuming elements while maintaining the frequency multiplication function.
3Manufacturing precision
If duty cycle calibration is performed using conventional methods, then duty cycle adjustment is achieved, but circuit area increases and bandwidth is limited
Solution Approach 1:
The patent merges the duty cycle calibration function with the frequency multiplication function into a single integrated circuit. By combining these functions, the patent achieves precise duty cycle calibration (50% accuracy) without requiring separate calibration circuits, thereby reducing overall circuit area while maintaining manufacturing precision.
Solution Approach 2:
The patent implements a dynamic feedback mechanism that automatically adjusts the duty cycle in real-time based on measured signal characteristics. This dynamic approach achieves high precision duty cycle calibration without requiring large static calibration circuits, thus reducing circuit area while maintaining accuracy.
Data Source
AI summary
A circuit and a method for adjusting a periodic input signal are provided. The circuit includes a duty cycle calibration (DCC) device, a phase adjusting device, and a duty cycle measurement (DCM) device. The DCC device is configured to generate a first signal and a second signal in response to the periodic input signal. The first signal and the second signal have different phases. The phase adjusting device is configured to receive the first signal and the second signal to generate a third signal by combining the first signal and the second signal based on a selection signal. The DCM device is configured to measure and adjust a duty cycle of the third signal so that the selection signal is adjusted to generate a periodic output signal. A frequency of the periodic output signal is twice that of the periodic input signal.