Duty-Cycle Correction Circuit Using Hierarchical Delay Adjustment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor integrated circuits and storage devices face challenges in accurately adjusting the duty cycle of clock signals, particularly in high-speed DDR communication, where precise timing adjustments are necessary to maintain data integrity and transfer efficiency.
Innovation Solution
The semiconductor integrated circuit incorporates a DCC circuit with a DCD circuit, a calculation circuit, and a DCA circuit to measure duty cycle errors, calculate delay values, and adjust clock signals, utilizing a combination of FINE and COARSE delay mechanisms to achieve precise timing corrections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single delay circuit is used to adjust clock signal timing, then the device complexity is reduced, but the measurement precision and adjustment accuracy of duty cycle cannot be achieved
Solution Approach 1:
The delay adjustment function is segmented into two independent circuits: a first delay circuit for coarse adjustment with first delay elements, and a second delay circuit for fine adjustment with second delay elements. This segmentation allows each circuit to be optimized for its specific adjustment range, achieving high precision duty cycle measurement without requiring a single overly complex circuit
Solution Approach 2:
The patent implements dynamic switching between coarse and fine adjustment modes based on the measured duty cycle error. The control circuit dynamically selects which delay circuit to activate, enabling the system to adapt its precision level to the current operational requirements while maintaining manageable circuit complexity
2Manufacturing precision
If multiple delay circuits are used to achieve precise timing adjustment, then the duty cycle adjustment accuracy is improved, but the device complexity increases
Solution Approach 1:
The timing adjustment system is divided into hierarchical levels: coarse adjustment handles large timing deviations, while fine adjustment handles minor precision requirements. This segmentation allows the system to achieve high manufacturing precision for timing adjustments without implementing a single complex high-precision circuit, thereby controlling overall device complexity
Solution Approach 2:
The patent applies partial action by using only the necessary level of precision for each adjustment scenario. The coarse delay circuit handles the majority of adjustment requirements, while the fine delay circuit is activated only when higher precision is needed, avoiding the complexity of continuously maintaining maximum precision capability
3Adaptability or versatility
If the delay amount of delay elements is increased to improve timing adjustment range, then the adaptability is improved, but the measurement precision of small delay differences deteriorates
Solution Approach 1:
The patent segments the delay adjustment into two ranges: the first delay circuit handles large delay adjustments for broad adaptability, while the second delay circuit handles small delay differences with high precision. This segmentation resolves the contradiction by allowing each circuit to be optimized for its specific range rather than requiring a single circuit to cover all possibilities
Solution Approach 2:
The control circuit dynamically switches between the first and second delay circuits based on the magnitude of timing adjustment required. This dynamic operation allows the system to maintain both wide adaptability for large adjustments and high measurement precision for small adjustments, as each circuit operates in its optimal performance regime
Data Source
AI summary
A semiconductor integrated circuit of an embodiment includes: a delay element array circuit in which a plurality of delay elements having a delay amount Tw are connected in series; a flip-flop group including a plurality of flip-flops each of which an input is connected to an output of a corresponding delay element; a delay element group configured to generate, from an input clock signal, a plurality of output clock signals each having a delay difference of a second delay amount smaller than the delay amount Tw; and a delay unit configured to set a third delay amount smaller than the second delay amount, and the delay element group and the delay unit are connected in series between an output terminal of an input signal CLK_DET and an input terminal of the flip-flop group.