Duty Cycle Correction Circuit for Odd-Divided High-Speed Clocks
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Solution Overview
Problem
Conventional duty cycle correction circuits in high-speed clock generation systems, such as those used in JESD204 serial interfaces, are limited by timing constraints that restrict the maximum frequency of the reference clock due to odd-valued divide ratios, falling short of the performance required for modern integrated circuits operating at high data rates.
Innovation Solution
A duty cycle correction circuit that includes a delay stage to output a delayed clock signal by one half-cycle of the reference clock and a logic function to generate an extended clock signal through a logical OR of the input and delayed clock signals, with a latch and flip-flop to latch and output the extended signal, and a multiplexer to alternate between the latch and flip-flop outputs in phases of the reference clock, effectively creating a full-cycle path for duty cycle correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional duty cycle correction circuit is used with odd-valued divide ratios, then the duty cycle can be corrected to 50%, but the timing constraints restrict the maximum reference clock frequency
Solution Approach 1:
The correction period is segmented into multiple phases (first correction period and second correction period) with different duty cycle correction amounts. This segmentation allows the circuit to distribute the correction workload over time, reducing the timing pressure on individual correction operations and enabling higher reference clock frequencies while maintaining accurate 50% duty cycle output.
Solution Approach 2:
The duty cycle correction amount is made dynamic rather than fixed. The circuit adjusts the correction amount based on the phase of the reference clock, applying different correction amounts during different correction periods. This dynamic adjustment allows the circuit to adapt to the timing constraints at high frequencies while still achieving precise duty cycle correction.
2Productivity
If the reference clock frequency is increased to support higher data rates, then the data transmission capability is improved, but the timing constraints in conventional duty cycle correction circuits become violated
Solution Approach 1:
The circuit performs preliminary duty cycle correction during a first correction period before the main operation phase, and then performs additional correction during a second correction period. This preliminary action approach allows the circuit to prepare the duty cycle correction in advance, ensuring that timing constraints are met even at high reference clock frequencies that support higher data rates.
Solution Approach 2:
The duty cycle correction is performed periodically with multiple correction periods within each reference clock cycle. By distributing corrections across multiple periodic intervals rather than requiring a single large correction, the circuit maintains timing constraint compliance while supporting higher data rates through increased reference clock frequency.
Data Source
AI summary
A duty cycle correction circuit, and method of operating the same, to correct the duty cycle of an input clock signal having a frequency divided-down from a reference clock by an odd-valued integer. A delay stage outputs the input clock signal delayed by one half-cycle of the reference clock, and a logic circuit outputs an extended clock signal by a logical OR of the input and delayed clock signals. A latch latches the extended clock signal when enabled by the reference clock, and a flip-flop latches the extended clock signal responsive to the reference clock. A gate selects the latch output or the flip-flop output based on the state of the delayed clock signal as an intermediate signal. A multiplexer generates the output clock by selecting between the intermediate signal and the input clock signal in alternating reference clock phases.