Duty Cycle Characterization by Averaging High and Low Intervals
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Solution Overview
Problem
Existing electronic circuits used for measuring timing quantities, such as duty cycle, face challenges due to complex timing measurement circuits that consume significant silicon area and require costly calibration, especially when characterizing high-speed signals.
Innovation Solution
A method and system for duty cycle characterization that involves determining a first duty cycle based on the interval of time a periodic signal is high and a second duty cycle based on the interval of time it is low, then averaging these duty cycles to improve measurement accuracy and reduce errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If timing measurement circuits are used to measure duty cycle, then measurement capability is provided, but silicon area consumption increases and calibration cost increases
Solution Approach 1:
The patent extracts the duty cycle measurement function from complex timing measurement circuits and implements it using simple digital logic components (flip-flops, XOR gates, counters). This separation allows the measurement capability to be achieved with minimal silicon area by removing unnecessary circuit complexity while retaining the essential measurement function.
Solution Approach 2:
The patent uses a copy-based approach where the periodic signal is captured and stored in flip-flops representing different time points within a period. By copying the signal state at specific moments (using D flip-flops triggered at different phases), the measurement is performed through digital logic comparison rather than analog timing circuits, reducing area requirements.
2Measurement precision
If timing measurement circuits are used to measure duty cycle, then measurement capability is provided, but calibration cost increases
Solution Approach 1:
The patent implements self-service by making the measurement system self-calibrating through digital logic. The system automatically determines duty cycle by comparing digital representations of signal states at different time points, eliminating the need for external calibration equipment or procedures. The measurement is performed purely through digital computation without requiring manual calibration adjustments.
Solution Approach 2:
The patent replaces analog timing measurement mechanisms with digital logic systems. Instead of using analog circuits that require calibration for accuracy, the invention uses digital flip-flops, latches, and logic gates that inherently provide stable, calibration-free measurements through their digital state representation and comparison capabilities.
3Device complexity
If single duty cycle measurement method is used, then measurement is simplified, but measurement accuracy decreases due to errors
Solution Approach 1:
The patent segments the duty cycle measurement into multiple independent measurements taken at different phases of the periodic signal. By dividing the measurement process into separate sampling events (using multiple D flip-flops triggered at different clock edges), the system captures the signal state at multiple points and combines these segmented measurements to compute the overall duty cycle, reducing the impact of errors in any single measurement.
Solution Approach 2:
The patent implements feedback by using the measured duty cycle information to adjust and refine the measurement process. The system continuously monitors the periodic signal and uses feedback from previous measurements to maintain accurate timing references and correct for any drift or errors, ensuring sustained measurement precision over time.
Data Source
AI summary
A method includes coupling a first signal to an impedance; determining a first average current of the first signal through the impedance over a first time, the first average current corresponding to a duty cycle of the first signal; coupling a second signal to the impedance; determining a second average current of the second signal through the impedance over a second time, the second average current corresponding to a first duty cycle of the second signal; determining the first duty cycle from the first average current and the second average current; determining a third average current of the second signal through the impedance over a third time, the third average current corresponding to a second duty cycle of the second signal; determining the second duty cycle from the first average current and the third average current; and averaging the first duty cycle and the second duty cycle.