Duty Cycle Corrector Circuit to Prevent Latch-Up
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional AC coupling self-bias inverter buffers face challenges in duty cycle correction, particularly when the driving capability of the latch circuit is weaker than the inverter buffers, leading to weak correction capabilities, and when it is stronger, resulting in latch-up problems where output signals may permanently stay at low or high levels.
Innovation Solution
The proposed duty cycle corrector incorporates a buffer circuit with upper and lower switch circuits between high and low voltage terminals, allowing for differential signal processing and current transmission/withdrawal to improve duty cycle correction and prevent latch-up issues by using complementary switch requirements for the upper and lower circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the driving capability of the latch circuit is increased to improve duty cycle correction capability, then the duty cycle correction capability is improved, but latch-up problems occur where output signals may permanently stay at low or high levels
Solution Approach 1:
The circuit is divided into four separate switch circuits (first upper, second upper, first lower, second lower) instead of using a single latch circuit. Each switch circuit independently controls current transmission or withdrawal based on specific input signal conditions, segmenting the monolithic latch function into modular components that can operate autonomously without causing mutual interference or latch-up.
Solution Approach 2:
The switch circuits are designed with dynamic control characteristics where each switch's on/off state is determined by real-time input signal conditions. The first upper switch circuit responds to rising edges of the first input signal, while the first lower switch circuit responds to falling edges, creating dynamic responsiveness that adapts to signal transitions and prevents static latch-up states.
2Reliability
If the driving capability of the latch circuit is increased to correct duty cycle, then the correction capability is improved, but the complexity of the circuit increases
Solution Approach 1:
Each switch circuit serves multiple functions: the first upper switch circuit both transmits current during rising edges and prevents latch-up through its controlled operation. The switch circuits collectively provide duty cycle correction, signal buffering, and latch-up prevention in a unified architecture, reducing the need for separate dedicated circuits for each function.
Solution Approach 2:
The switch circuits automatically regulate their own operation based on input signal characteristics without requiring external control mechanisms. The circuits self-adjust their current transmission or withdrawal based on the detected signal edges, eliminating the need for additional control logic or monitoring circuits that would increase system complexity.
3Device complexity
If conventional AC coupling self-bias inverter buffers are used, then the circuit structure is simple, but the duty cycle correction capability is weak when the latch circuit driving capability is weak
Solution Approach 1:
The four switch circuits are designed with asymmetric control characteristics tailored to their specific functions. The upper switch circuits are optimized for current transmission during rising edges, while the lower switch circuits are optimized for current withdrawal during falling edges. This asymmetric design allows each circuit to be optimized for its specific duty cycle correction task rather than using a symmetric, generic latch structure.
Data Source
AI summary
Disclosed is a duty cycle corrector including a buffer circuit, an upper circuit, and a lower circuit. The buffer circuit includes: a first buffer circuit receiving a first input signal and thereby outputting a second output signal to a second output terminal; a second buffer circuit receiving a second input signal and thereby outputting a first output signal to a first output terminal; and a latch circuit coupled between the first and second output terminals. The upper circuit is coupled between a high voltage terminal and the buffer circuit and transmits current to the first and second output terminals according to each of the first and second input signals. The lower circuit is coupled between the buffer circuit and a low voltage terminal and withdraws current flowing through the first and second output terminals according to each of the first and second input signals.