Duty Cycle Clock Control Using Looped Unit Delay Circuits
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Solution Overview
Problem
Conventional duty cycle controllers require large area delay circuits to achieve half-period delays, which is physically challenging in chip design and difficult to accurately control at high frequencies due to process variations.
Innovation Solution
A delay circuit comprising a unit delay circuit and a loop counter that adjusts delay time by passing the signal through the unit delay circuit multiple times, allowing for reduced area and stable delay time control across a wide frequency range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large delay circuit is used to delay the clock signal by half period, then the duty ratio control accuracy is improved, but the circuit area increases
Solution Approach 1:
The delay circuit is divided into multiple unit delay circuits connected in series. Each unit delay circuit contributes a portion of the total delay, allowing the achievement of half-period delay through composition of smaller delay units rather than a single large delay circuit.
Solution Approach 2:
The unit delay circuits are designed to be identical and reusable. The same unit delay circuit structure is instantiated multiple times to achieve the required total delay, providing a universal building block that simplifies design and reduces area compared to a custom large delay circuit.
2Manufacturing precision
If a large delay circuit is used to delay the clock signal, then the delay time control is improved, but the difficulty of arrangement on chip increases
Solution Approach 1:
The delay circuit is segmented into multiple identical unit delay circuits. This segmentation allows for systematic arrangement on the chip, where each unit can be placed in a regular pattern, simplifying the overall layout and arrangement process compared to placing a single large irregular delay circuit.
Solution Approach 2:
Each unit delay circuit is designed with consistent local characteristics, ensuring uniform delay contribution from each unit. This local uniformity simplifies the arrangement process as each unit can be treated identically during placement and routing, reducing the complexity of chip arrangement.
3Productivity
If the operating frequency is increased, then the productivity is improved, but the accuracy of delay time control in large delay circuit deteriorates
Solution Approach 1:
By segmenting the delay circuit into multiple unit delay circuits, the total delay is distributed across several stages. This segmentation allows each unit to operate at higher frequencies with better timing control, as each unit experiences less cumulative process variation and can be optimized for high-frequency operation.
Solution Approach 2:
The delay circuit parameters are optimized at the unit level rather than for a large circuit. Each unit delay circuit can be designed with parameters specifically optimized for high-frequency operation, and the cumulative effect of multiple units achieves the required total delay while maintaining accuracy at high operating frequencies.
Data Source
AI summary
In an embodiment, a duty cycle controller comprises a delay circuit configured to output the feedback clock signal by delaying an output clock signal combined from an input clock signal and a feedback clock signal by a predetermined delay time, wherein the delay circuit comprises a unit delay circuit configured to delay the output clock signal by a time less than the predetermined delay time and configured to delay the feedback clock signal by the predetermined delay time by letting the output clock signal pass the unit delay circuit as many as a predetermined loop count.