Duty Cycle Corrector With Low-Frequency Correction Blocking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Duty cycle correctors in semiconductor memory devices face challenges in preventing excessive duty cycle correction, particularly when dealing with low frequency input clock signals, which can lead to distortion and loss of output clock pulses.
Innovation Solution
A duty cycle corrector is designed with a low frequency detector and control circuit that blocks duty control signals when the input clock signal is below a predetermined frequency, preventing excessive duty cycle correction by disabling the common mode control circuit, thereby maintaining signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If duty cycle correction is continuously performed on low frequency input clock signal, then duty cycle adjustment is achieved, but output clock signal distortion occurs and pulses are lost
Solution Approach 1:
The duty cycle corrector dynamically adjusts its operation based on the frequency of the input clock signal. A frequency detection circuit monitors the input signal frequency and controls the duty cycle correction amplifier accordingly. When the input frequency is below a predetermined threshold, the correction is restricted or disabled, preventing excessive common mode variation that would cause signal distortion. This dynamic adaptation resolves the contradiction by making the correction intensity dependent on operating conditions.
Solution Approach 2:
The system changes the operational parameters of the duty cycle correction amplifier based on the input signal frequency. Specifically, the common mode control is adjusted according to frequency thresholds - at low frequencies, the common mode variation is limited to prevent distortion, while at higher frequencies, full correction is applied. This parameter change approach allows the system to optimize duty cycle accuracy without compromising signal integrity in different operating regimes.
2Reliability
If duty cycle correction is performed on high frequency input clock signal, then duty cycle is corrected without excessive variation, but low frequency signals require greater adjustment that causes distortion
Solution Approach 1:
The frequency detection and conditional control mechanism enables the duty cycle corrector to adapt its correction strength dynamically. For high frequency signals, the system applies standard correction achieving good duty cycle accuracy. For low frequency signals, the system detects the frequency condition and modifies the correction approach to prevent excessive common mode variation, thus maintaining signal quality despite the greater adjustment needed.
Solution Approach 2:
The correction approach is localized according to frequency bands. Different correction strategies are applied to different frequency ranges: high frequency signals receive standard duty cycle correction, while low frequency signals receive restricted or modified correction. This localized quality approach ensures optimal performance for each frequency range without compromising overall system reliability.
Data Source
AI summary
Provided is a duty cycle corrector including a low frequency detector detecting whether an input clock signal frequency is less than or greater than a predetermined frequency. If less than, a common mode control circuit controlling a common mode of a duty cycle correction amplifier amplifying the input clock signal is disabled. The duty cycle corrector may include a column address strobe (CAS) latency determination unit that determines whether a CAS latency is greater than or less than a predetermined value instead of the low frequency detector.