Duty Cycle Correction Circuit With Monotonic Delay Selection
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Solution Overview
Problem
Existing duty cycle correction circuits face limitations in maintaining monotonicity, adjusting resolution, and power consumption, leading to potential device malfunction and impractical applications due to variations in clock signal frequency and non-uniform step sizes.
Innovation Solution
A method and circuit for duty cycle correction that generates intermediate delayed signals, selects appropriate signals based on unit delays, and adjusts duty cycles using OR and AND logic to maintain a consistent duty cycle, ensuring monotonicity and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing duty correction circuits are used to correct duty cycle, then duty cycle adjustment is achieved, but monotonicity cannot be maintained due to device mismatch in delay elements
Solution Approach 1:
The delay line is segmented into multiple delay elements (first delay element, second delay element, etc.) that can be independently controlled. This segmentation allows selective activation of delay elements based on the required correction amount, ensuring monotonicity even with device mismatch. The controller activates delay elements in a controlled sequence to maintain monotonic delay adjustment.
Solution Approach 2:
The circuit dynamically selects and activates specific delay elements based on the input signal characteristics and required correction. The controller dynamically adjusts which delay elements are active, allowing the system to adapt to varying duty cycle errors while maintaining monotonicity through controlled activation sequences.
2Measurement precision
If duty correction circuits are designed with fine adjustment resolution, then correction precision is improved, but power consumption and circuit size increase
Solution Approach 1:
The delay correction is segmented into discrete delay elements with uniform step sizes. Instead of using a single fine-adjustment mechanism that would consume high power, the circuit uses multiple coarser delay elements that can be selectively activated. This segmentation achieves fine overall resolution through combination while keeping individual element power consumption low.
Solution Approach 2:
The circuit applies partial delay correction by activating only the necessary number of delay elements required to achieve the target duty cycle. Rather than continuously adjusting all delay elements, the controller activates only the minimal set needed, reducing power consumption while maintaining the required correction resolution.
3Measurement precision
If duty correction circuits are designed with fine adjustment resolution, then correction precision is improved, but circuit area increases
Solution Approach 1:
The delay line is divided into multiple delay elements that can be shared between different signal paths. This segmentation allows the circuit to achieve fine adjustment resolution through selective combination of delay elements rather than duplicating full delay lines for each adjustment level, thereby reducing overall circuit area.
Solution Approach 2:
The delay elements are designed to serve multiple functions: they can be selectively activated for different correction amounts, and the same delay elements can be used for both monotonicity maintenance and fine resolution adjustment. This multi-functionality reduces the need for separate circuit components, minimizing circuit area while maintaining high adjustment resolution.
4Adaptability or versatility
If delay elements are activated to correct duty cycle, then duty correction range is increased, but monotonicity fails due to device mismatch
Solution Approach 1:
The delay correction range is achieved through segmentation into multiple delay elements with uniform step sizes. The controller activates these segmented elements in a controlled sequence, ensuring that even with device mismatch, the overall delay adjustment remains monotonic. Each segment contributes a predictable amount of delay, maintaining monotonicity across the full correction range.
Solution Approach 2:
The delay elements are pre-configured with uniform step sizes and the controller has predetermined activation sequences to maintain monotonicity. This preliminary arrangement ensures that as the duty correction range is expanded by activating more delay elements, monotonicity is preserved through pre-planned activation patterns rather than requiring real-time complex control.
Data Source
AI summary
The inventive concepts relate to methods for duty cycle correction of an input signal and circuits thereof. The method comprising following operations of generating, a plurality of intermediate delayed input signals, each delayed by at least a unit delay, through a delay line driven by the input signal, selecting from among the plurality of delayed input signals, through a first control signal, where the selection is based on number of unit delays in the input signal, generating at least an incremented duty signal and a decremented duty signal based on the selected delayed signals and the input signal, generating, a corrected duty cycle based on the selection of at least one of: the incremented duty cycle or decremented duty cycle by providing a second control signal. The inventive concepts offer low power consumption and low area for correction or adjustment of the duty cycle of the input signal with higher probability or guaranteed monotonicity.