Clock Duty Cycle Adjuster Setting With Monitor Offset Boundaries
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Solution Overview
Problem
Semiconductor memories face issues with duty cycle distortion in clock timing, leading to erroneous operations due to deviations from the ideal 50% duty cycle, which existing duty cycle adjuster circuits may not adequately address without accurate settings.
Innovation Solution
The implementation of a duty cycle monitor (DCM) and duty cycle adjuster (DCA) feature within a semiconductor device's mode register, allowing for precise adjustment of internal clock duty cycles through programmable DCA codes and step sizes to compensate for systemic duty cycle errors, using a DCM sequence to determine optimal DCA settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If duty cycle adjuster circuits are used to adjust internal clock duty cycle, then duty cycle distortion is reduced, but the adjustment is insufficient unless the adjuster circuits are set accurately
Solution Approach 1:
The patent implements a feedback mechanism where the memory device measures its own clock duty cycle using internal circuitry and communicates the measured duty cycle information back to the memory controller. The memory controller then uses this feedback to calculate and determine the appropriate duty cycle adjuster setting, creating a closed-loop system that automatically compensates for duty cycle distortion without requiring complex manual calibration procedures.
2Measurement precision
If manual calibration of duty cycle adjuster is performed, then duty cycle can be adjusted, but it requires accurate settings that are difficult to achieve
Solution Approach 1:
The memory device performs self-measurement of its clock duty cycle using internal measurement circuitry integrated within the device. This eliminates the need for external measurement equipment and simplifies the calibration process, as the device automatically characterizes its own duty cycle distortion and communicates this information to the controller for automatic setting determination.
3Adaptability or versatility
If duty cycle adjuster settings are made programmable, then flexibility in adjustment is improved, but the complexity of determining optimal settings increases
Solution Approach 1:
The system uses feedback from the memory device's measured duty cycle information to enable the memory controller to automatically calculate the optimal programmable setting for the duty cycle adjuster. This feedback-driven approach maintains flexibility while eliminating the complexity of manual optimization, as the controller dynamically determines the correct setting based on actual measured conditions.
Data Source
AI summary
Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.