Duty Cycle Detector Offset Cancellation for Clock Distortion Correction
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Solution Overview
Problem
Duty cycle distortion in clock signals used in electrical circuit devices leads to timing issues and unreliable performance, especially at high input/output speeds, and existing duty cycle detector calibration methods struggle with offset errors, making it difficult to accurately correct for distortions.
Innovation Solution
The implementation of a duty cycle calibration circuit that includes a duty cycle detector and adjuster, capable of automatically canceling offset errors without recalibration, by performing initial and flipped searches to determine a final code value that corrects duty cycle distortions, thereby ensuring accurate adjustment of clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DCD circuit calibration is performed to determine a trim value to cancel DCD offset, then offset error correction is achieved, but the process becomes complex and requires direct sensing at the clock source which is difficult in some applications
Solution Approach 1:
The patent introduces an intermediary calibration approach where the DCD circuit calibration is performed using available clock signals at the sensing location rather than requiring direct sensing at the clock source. This intermediary method uses the relationship between system clock and complementary clock signals to indirectly determine the required trim value, simplifying the calibration process while maintaining accuracy.
Solution Approach 2:
The patent replaces the complex direct sensing and manual calibration mechanism with an automated digital calibration system. The system uses digital signal processing to compare clock signals, automatically calculate the DCD offset, and determine the appropriate trim value without requiring physical access to the clock source or complex manual adjustment procedures.
2Reliability
If DCD circuit has offset error, then duty cycle distortion detection is compromised, but recalibration is difficult without direct access to clock source
Solution Approach 1:
The patent implements a self-service calibration mechanism where the DCD circuit automatically performs its own calibration using the clock signals already present in the system. The circuit uses the system clock and complementary clock signals to self-determine the offset error and self-adjust the trim value, eliminating the need for external calibration equipment or direct access to the clock source.
Solution Approach 2:
The patent employs feedback mechanisms where the DCD circuit continuously monitors the relationship between clock signals and uses this information to automatically adjust the trim value. The calibration process uses feedback from the detected duty cycle differences to iteratively refine the offset correction, ensuring reliable operation without manual intervention.
3Productivity
If input/output speeds increase, then timing margins are reduced, but duty cycle distortion becomes more challenging to reduce
Solution Approach 1:
The patent applies preliminary action by performing DCD circuit calibration and offset correction before the actual high-speed data transmission begins. The system pre-determines the appropriate trim value using the calibration routine, ensuring that the DCD circuit is optimally configured before facing the challenges of high-speed operation and reduced timing margins.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the trim value based on the detected duty cycle distortion. The system monitors the clock signal characteristics and modifies the DCD circuit parameters (trim value) to compensate for distortion, enabling accurate duty cycle detection even at high input/output speeds where timing margins are compressed.
Data Source
AI summary
Several embodiments of electrical circuit devices and systems with a duty cycle correction apparatus that includes a duty cycle adjustment circuit that is configured to adjust a duty cycle of the input clock signal based on an averaged code value. The duty cycle correction apparatus includes a duty cycle detector circuit that receives first and second clock signals from a clock distribution network. The duty cycle detector is configured to output a duty cycle status signal that indicates whether the first clock signal is above or below a 50% duty cycle based on a comparison of the first clock signal to the second clock signal. The duty cycle correction apparatus also includes a counter logic circuit configured to determine the average code value, and the counter logic circuit automatically cancels an offset of the duty cycle detector when determining the averaged code value.