Duty Cycle Adjuster Setting With Monitor Offset Boundaries
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Solution Overview
Problem
Semiconductor memories face issues with duty cycle distortion in internal clock signals, leading to erroneous operations due to deviations from the ideal 50% duty cycle, which existing duty cycle adjuster circuits may not adequately address without accurate settings.
Innovation Solution
The implementation of a duty cycle monitor (DCM) and duty cycle adjuster (DCA) feature within a mode register allows for precise monitoring and adjustment of internal data clocks, enabling accurate compensation for duty cycle errors through programmable opcode settings, ensuring optimal timing adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If duty cycle adjuster circuits are used to adjust internal clock duty cycle, then duty cycle distortion is reduced, but the adjustment is insufficient unless the adjuster circuits are set accurately
Solution Approach 1:
The patent implements a feedback mechanism where the memory device measures its own clock duty cycle using duty cycle monitor circuits and uses this measurement to automatically adjust the duty cycle adjuster circuits. The memory device reads back duty cycle measurement values, determines appropriate adjustment settings, and programs these settings into the adjuster circuits, creating a closed-loop system that eliminates the need for external manual calibration.
Solution Approach 2:
The memory device performs self-calibration of its clock duty cycle by autonomously measuring the duty cycle distortion, determining the necessary correction, and configuring its own duty cycle adjuster circuits without requiring external calibration equipment or manual intervention. This self-service capability allows the device to automatically compensate for process variations and ensure accurate duty cycle.
2Reliability
If manual calibration methods are used to set duty cycle adjuster circuits, then external equipment and time are required, but the process becomes complex and time-consuming
Solution Approach 1:
The memory device autonomously performs the entire duty cycle calibration process by internally measuring duty cycle distortion using monitor circuits, calculating the necessary correction settings, and automatically programming these settings into the duty cycle adjuster circuits. This eliminates the need for external calibration equipment and manual intervention, significantly simplifying the calibration process.
Solution Approach 2:
The patent extracts the calibration function from the external calibration process and integrates it directly into the memory device's internal operation. By incorporating duty cycle monitor circuits and automatic adjustment logic within the memory device, the calibration process is transformed from an external complex procedure into an internal automated function.
3Reliability
If duty cycle adjuster circuits are implemented in memory devices, then duty cycle distortion can be compensated, but existing circuits may not improve duty cycle sufficiently without accurate settings
Solution Approach 1:
The patent implements a feedback mechanism where duty cycle monitor circuits continuously measure the actual duty cycle of internal clocks, and this measurement information is used to automatically adjust the duty cycle adjuster circuits. The system reads duty cycle measurement values, determines appropriate correction settings, and programs these settings into the adjuster circuits, ensuring precise duty cycle correction without requiring external calibration.
Solution Approach 2:
The patent changes the operating parameters of the duty cycle adjuster circuits based on measured duty cycle distortion. By dynamically adjusting the adjuster circuit settings according to actual duty cycle measurements rather than using fixed manufacturer defaults, the system achieves precise duty cycle correction that adapts to specific device characteristics and operating conditions.
Data Source
AI summary
Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.