Duty-Cycle Correction Circuit Using Periodic Delayed Clock Control
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Solution Overview
Problem
Conventional duty-cycle correction circuits in DDR memory systems require a long time to correct duty-cycle distortions and consume significant power due to PVT variations, affecting timing margins.
Innovation Solution
A duty-cycle correction circuit and method that utilizes a target clock and delayed clocks to generate a duty-cycle control code, adjusting the duty-cycle of the source clock during a preset correction period, thereby reducing correction time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional duty-cycle correction circuit continuously operates to correct duty-cycle distortion, then the duty-cycle accuracy is improved, but the power consumption increases and correction time is extended
Solution Approach 1:
The duty-cycle correction circuit operates periodically rather than continuously. The control unit enables the delayed clock generation unit only during a preset duty-cycle correction period, and disables it during periods except for the correction period. This periodic operation reduces power consumption while maintaining duty-cycle accuracy through timely corrections.
Solution Approach 2:
The correction circuit performs duty-cycle correction in advance during preset correction periods before the actual data operations occur. By proactively correcting the duty-cycle distortion beforehand, the circuit ensures accurate timing margins are established prior to critical operations, maintaining precision without continuous operation.
2Measurement precision
If a conventional duty-cycle correction circuit continuously operates to correct duty-cycle distortion, then the duty-cycle accuracy is improved, but the correction time is extended
Solution Approach 1:
The circuit performs corrections periodically during preset correction periods rather than continuously. This approach concentrates correction operations into specific time windows, reducing the overall correction time while maintaining accuracy through sufficient correction depth during each active period.
Solution Approach 2:
The control unit enables the delayed clock generation unit only when needed for correction, skipping operation during non-correction periods. This rushing through of correction operations during brief enabled periods reduces total correction time while achieving the necessary accuracy adjustment.
3Reliability
If the delayed clock generation unit operates continuously, then the duty-cycle can be corrected at any time, but the power consumption increases
Solution Approach 1:
The delayed clock generation unit is enabled periodically during preset correction periods and disabled during other periods. This periodic operation maintains duty-cycle correction availability when needed while significantly reducing power consumption during non-correction periods when the system operates normally.
Solution Approach 2:
The control unit automatically manages the enabled/disabled states of the delayed clock generation unit based on whether correction is needed. The system self-regulates its operation to perform corrections only when duty-cycle distortion requires adjustment, eliminating the need for continuous operation and reducing power consumption.
Data Source
AI summary
A duty-cycle correction circuit may include a delayed clock generation unit suitable for generating a plurality of delayed clocks by delaying a target clock by different delay values, an up/down signal generation unit suitable for selecting a delayed clock having a delay value corresponding to a first section of the target clock, and generating an up/down signal according to the lengths of a second section of the target clock and the first section of the selected delayed clock, a duty-cycle control code generation unit suitable for generating a duty-cycle control code in response to the up/down signal, a duty-cycle adjusting unit suitable for generating a duty-cycle correction clock by adjusting the duty-cycle of a source clock, and a control unit suitable for enabling the delayed clock generation unit during a duty-cycle correction period, and disabling the delayed clock generation unit during periods except for the duty-cycle correction period.