Duty Cycle Calibration Circuit With Temperature-Compensated Phase Adjustment
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Solution Overview
Problem
High-speed circuits face significant power consumption issues due to the use of two delay adjustment units for duty cycle calibration, which is not conducive to designing low-power circuits.
Innovation Solution
A duty cycle calibration circuit that converts a single-ended clock signal to differential and then back to single-ended, incorporating a temperature compensation mechanism to adjust voltage and phase, reducing power consumption while maintaining duty cycle consistency across temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If two delay adjustment units are used for duty cycle calibration, then the duty cycle can be calibrated, but the power consumption increases significantly
Solution Approach 1:
The patent segments the duty cycle calibration into two independent paths: one path (first delay adjustment unit) handles the rising edge with coarse delay adjustment, and the other path (second delay adjustment unit) handles the falling edge with fine delay adjustment. This segmentation allows each unit to operate independently and efficiently, reducing the total power consumption compared to using two units for both edges
Solution Approach 2:
The patent applies partial action by using only one unit (the second delay adjustment unit) for fine-tuning the falling edge delay, while the first delay adjustment unit handles the rising edge. The fine delay adjustment is applied selectively only where needed, rather than duplicating full adjustment capabilities in both paths, thereby reducing overall power consumption
2Measurement precision
If delay adjustment units are used for duty cycle calibration, then the duty cycle can be adjusted, but the circuit complexity increases
Solution Approach 1:
The patent divides the calibration circuit into distinct functional segments: a first delay adjustment unit for coarse adjustment of the rising edge, a second delay adjustment unit for fine adjustment of the falling edge, and a multiplexer for selective signal routing. This segmentation organizes the complexity into manageable, independent modules that can be designed and optimized separately
Solution Approach 2:
The patent introduces dynamic control through a multiplexer that selectively routes signals based on calibration mode. The multiplexer dynamically switches between direct output and delayed output paths, allowing the circuit to adapt its complexity level based on whether calibration is needed or normal operation is required
3Measurement precision
If traditional delay adjustment units are used, then duty cycle calibration is achieved, but temperature variations affect duty cycle consistency
Solution Approach 1:
The patent introduces delay calibration units as intermediary components between the clock signal paths and the output. These units act as mediators that compensate for temperature-induced delay variations by providing adjustable delay compensation, thereby maintaining consistent duty cycle across different temperature conditions
Solution Approach 2:
The patent employs parameter changes by making the delay characteristics of the delay adjustment units可调 (adjustable). By changing the delay parameters of these units based on temperature compensation requirements, the system maintains consistent duty cycle performance across varying temperature conditions
Data Source
AI summary
A duty cycle calibration circuit includes delay, temperature compensation, differential, and phase adjustment units. The delay adjustment unit receives a single-ended input clock signal to be calibrated and an adjustment voltage and outputs a single-ended clock signal adjusted by the adjustment voltage. The temperature compensation adjustment unit determines the adjustment voltage output by the temperature compensation adjustment unit, and provides the adjustment voltage to the delay adjustment unit to eliminate the influence of the temperature on the duty cycle. The differential adjustment unit converts the single-ended clock signal into a differential clock signal, and adjusts delay of the differential clock signal. The phase adjustment unit receives the adjusted differential clock signal to adjust its phase and converts it into a single-ended output clock signal after phase adjustment, and makes rising and falling edges of the single-ended output clock signal correspond to rising edges of the adjusted differential clock signal respectively.