Duty Cycle Correction Circuitry Using Prime-Ratio Clock Sampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing techniques for correcting clock duty cycles in DDR memory systems are either too slow, large, or inaccurate, particularly when dealing with multiple clock signals, and conventional asynchronous sampling methods can introduce significant errors due to non-random sampling assumptions.
Innovation Solution
A duty cycle correction circuitry that uses a well-controlled asynchronous sampling clock to periodically sample the target clock signal at a prime number ratio, allowing for precise measurement and correction of duty cycle errors based on a single measurement cycle, thereby minimizing the number of samples required and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If RC filter techniques are used to correct clock duty cycle, then duty cycle precision is improved, but correction speed becomes unacceptably slow and device size increases
Solution Approach 1:
The patent replaces the mechanical RC filter system with a digital measurement and correction system. Instead of using physical resistors and capacitors to slowly filter and measure duty cycle, the invention uses digital counters and logic circuits to rapidly measure the clock signal characteristics and generate correction signals, achieving both high precision and fast correction speed.
Solution Approach 2:
The patent introduces an intermediary measurement system that uses a high-frequency reference clock and counter to indirectly measure the duty cycle of the target clock signal. This intermediary approach allows for rapid digital measurement without the speed limitations of direct RC filtering, while maintaining measurement precision through the use of multiple clock cycles for averaging.
2Measurement precision
If RC filter techniques are used to correct clock duty cycle, then duty cycle precision is improved, but device size and implementation cost increase
Solution Approach 1:
The patent replaces the mechanical RC filter system with a digital measurement and correction system. Instead of using physical resistors and capacitors to slowly filter and measure duty cycle, the invention uses digital counters and logic circuits to rapidly measure the clock signal characteristics and generate correction signals, achieving both high precision and fast correction speed.
Solution Approach 2:
The patent creates a universal duty cycle correction system that can handle multiple clock signals using the same core measurement and correction logic. The system uses a reference clock and counter that can be configured to measure different target clock frequencies, making the device scalable and reducing overall complexity when correcting multiple signals compared to using separate RC filters for each signal.
3Speed
If asynchronous sampling is used to measure duty cycle, then measurement speed is improved, but measurement accuracy deteriorates due to non-random sampling errors
Solution Approach 1:
The patent uses periodic sampling synchronized to a reference clock that runs at a prime number multiple of the target clock frequency. This periodic action ensures that over one complete measurement period, the sampling points uniformly cover the entire duty cycle of the target clock, eliminating systematic sampling errors while maintaining fast measurement speed through the use of a high-frequency reference clock.
Solution Approach 2:
The patent changes the sampling parameters by using a reference clock with a prime number frequency ratio to the target clock. This parameter choice ensures that the sampling points are distributed uniformly across the duty cycle over one measurement period, transforming the sampling process from potentially biased asynchronous sampling to uniformly distributed periodic sampling that eliminates systematic errors.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Examples may include techniques for using a sample clock to measure a duty cycle by periodic sampling a target clock signal based on a prime number ratio of a reference clock frequency. The reference clock frequency used to set a measurement cycle time over which the duty cycle is to be measured. A magnitude of a duty cycle error as compared to a programmable target duty cycle is determined based on the measured duty cycle and the duty cycle is adjusted based, at least in part, on the magnitude of the duty cycle error.