Duty Cycle Calibration Circuit Using High-Frequency Pulse Counting
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Solution Overview
Problem
Existing duty cycle calibration methods suffer from inaccurate measurements due to the influence of reference clock signals, leading to low precision in duty cycle calibration.
Innovation Solution
A duty cycle calibration circuit utilizing a counting clock signal with a higher frequency than the calibration clock signal to accurately count pulses in high and low states, comparing the current duty cycle with a target duty cycle, and adjusting the input clock signal through a control signal to achieve precise calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference clock signal is used to measure the duty cycle of a calibration clock signal, then the measurement process can be implemented, but the measurement accuracy deteriorates due to the influence and potential instability of the reference clock signal
Solution Approach 1:
The patent introduces a counting clock signal as an intermediary measurement tool. Instead of directly comparing the calibration clock signal with a potentially unstable reference clock signal, the system uses a high-frequency counting clock signal to count the number of high-level and low-level states of the calibration clock signal. This intermediary counting mechanism isolates the measurement process from reference clock instability, thereby improving measurement accuracy while maintaining reliability.
2Measurement precision
If a high-frequency counting clock signal is used to count pulses, then the measurement precision of duty cycle is improved, but the device complexity increases due to additional counting and control circuits
Solution Approach 1:
The patent divides the duty cycle measurement process into distinct functional segments: a counting unit that counts high-level and low-level states separately, a control unit that manages the counting process and generates control signals, and a duty cycle adjustment unit that modifies the input clock signal. This segmentation allows each component to perform its specific function efficiently, improving measurement precision while organizing the complexity into manageable, modular units.
3Measurement precision
If the duty cycle calibration process is made more precise through multiple counting operations, then the calibration accuracy is improved, but the calibration time increases
Solution Approach 1:
The patent employs periodic counting operations where the counting unit repeatedly counts the high-level and low-level states of the calibration clock signal over multiple periods. The control unit coordinates these periodic counting operations and uses the accumulated data to calculate the duty cycle with high precision. This periodic approach allows accurate measurement over extended time while maintaining systematic control, balancing calibration accuracy with time efficiency.
Data Source
AI summary
Provided are a duty cycle calibration circuit and method, a chip, and an electronic device. In the duty cycle calibration circuit, through a counting clock signal having a higher clock signal frequency than a calibration clock signal, a counting unit is configured to acquire a number of counting pulses generated in a high-level state and a low-level state of the calibration clock signal within a preset counting period, so as to obtain an actual duty cycle of the calibration clock signal. Compared with a method of acquiring a duty cycle of a calibration clock signal by comparing the calibration clock signal with a reference clock signal, inaccurate measurement of the duty cycle of the calibration clock signal after the reference clock signal is affected can be overcome. Therefore, accuracy of measurement of the duty cycle can be improved, and precision of calibration of the duty cycle can be improved accordingly.